[llvm-commits] XOP encoding patch

[Eli Friedman]

On Thu, Dec 8, 2011 at 12:49 PM, Jan Sjodin <jan_sjodin at yahoo.com> wrote:
> This patch handles the encoding of XOP instructions. I included one
> instruction for each kind including a test.

+multiclass xop4opimm<bits<8> opc, string OpcodeStr> {
+  def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
+           (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),

As discussed on IRC, you want i8imm here, not i32i8imm.

+      // If there is an additional 5th operand it must be an immediate, which
+      // is encoded in bits[3:0]
+      if(CurOp != NumOps) {
+	const MCOperand &MIMM = MI.getOperand(CurOp++);
+	if(MIMM.isImm()) {
+	  unsigned Val = MIMM.getImm();
+	  assert(Val < 16 && "Immediate operand value out of range");
+	  RegNum |= Val;
+	}
+      }

No tabs, please.

This patch doesn't include disassembler support; are you planning to add that?

Someone more familiar with the x86 instruction patterns should
probably review this in addition.

-Eli