[llvm-commits] [llvm] r144301 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/thumb-diagnostics.s
Jim Grosbach
grosbach at apple.com
Thu Nov 10 11:18:01 PST 2011
Author: grosbach
Date: Thu Nov 10 13:18:01 2011
New Revision: 144301
URL: http://llvm.org/viewvc/llvm-project?rev=144301&view=rev
Log:
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/basic-arm-instructions.s
llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=144301&r1=144300&r2=144301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 10 13:18:01 2011
@@ -544,6 +544,14 @@
let ParserMatchClass = Imm0_31AsmOperand;
}
+/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
+def Imm0_32AsmOperand: AsmOperandClass { let Name = "Imm0_32"; }
+def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
+ return Imm >= 0 && Imm < 32;
+}]> {
+ let ParserMatchClass = Imm0_32AsmOperand;
+}
+
/// imm0_255 predicate - Immediate in the range [0,255].
def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
@@ -5001,5 +5009,14 @@
// encoding. It seems we should be able to do that sort of thing
// in tblgen, but it could get ugly.
def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
- (ins GPR:$Rd, GPR:$Rm, imm1_32:$imm, pred:$p,
+ (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
+ cc_out:$s)>;
+def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
+ (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
+ cc_out:$s)>;
+def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
+ (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
+ cc_out:$s)>;
+def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
+ (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
cc_out:$s)>;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=144301&r1=144300&r2=144301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Nov 10 13:18:01 2011
@@ -602,6 +602,14 @@
int64_t Value = CE->getValue();
return Value > 0 && Value < 33;
}
+ bool isImm0_32() const {
+ if (Kind != k_Immediate)
+ return false;
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ if (!CE) return false;
+ int64_t Value = CE->getValue();
+ return Value >= 0 && Value < 33;
+ }
bool isImm0_65535() const {
if (Kind != k_Immediate)
return false;
@@ -1217,6 +1225,11 @@
Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
}
+ void addImm0_32Operands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ addExpr(Inst, getImm());
+ }
+
void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
addExpr(Inst, getImm());
@@ -4542,14 +4555,28 @@
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
// Handle the MOV complex aliases.
- case ARM::ASRi: {
- unsigned Amt = Inst.getOperand(2).getImm() + 1;
- unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt);
+ case ARM::ASRi:
+ case ARM::LSRi:
+ case ARM::LSLi:
+ case ARM::RORi: {
+ ARM_AM::ShiftOpc ShiftTy;
+ unsigned Amt = Inst.getOperand(2).getImm();
+ switch(Inst.getOpcode()) {
+ default: llvm_unreachable("unexpected opcode!");
+ case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
+ case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
+ case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
+ case ARM::RORi: ShiftTy = ARM_AM::ror; break;
+ }
+ // A shift by zero is a plain MOVr, not a MOVsi.
+ unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
+ unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
MCInst TmpInst;
- TmpInst.setOpcode(ARM::MOVsi);
+ TmpInst.setOpcode(Opc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty
+ if (Opc == ARM::MOVsi)
+ TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
TmpInst.addOperand(Inst.getOperand(5)); // cc_out
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=144301&r1=144300&r2=144301&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Thu Nov 10 13:18:01 2011
@@ -261,9 +261,11 @@
@------------------------------------------------------------------------------
asr r2, r4, #32
asr r2, r4, #2
+ asr r2, r4, #0
@ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1]
@ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1]
+@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@------------------------------------------------------------------------------
@@ -787,11 +789,28 @@
@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80]
@------------------------------------------------------------------------------
-@ FIXME: LSL
+@ LSL
@------------------------------------------------------------------------------
+ lsl r2, r4, #31
+ lsl r2, r4, #1
+ lsl r2, r4, #0
+
+@ CHECK: lsl r2, r4, #31 @ encoding: [0x84,0x2f,0xa0,0xe1]
+@ CHECK: lsl r2, r4, #1 @ encoding: [0x84,0x20,0xa0,0xe1]
+@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
+
+
@------------------------------------------------------------------------------
-@ FIXME: LSR
+@ LSR
@------------------------------------------------------------------------------
+ lsr r2, r4, #32
+ lsr r2, r4, #2
+ lsr r2, r4, #0
+
+@ CHECK: lsr r2, r4, #32 @ encoding: [0x24,0x20,0xa0,0xe1]
+@ CHECK: lsr r2, r4, #2 @ encoding: [0x24,0x21,0xa0,0xe1]
+@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
+
@------------------------------------------------------------------------------
@ MCR/MCR2
@@ -1320,6 +1339,18 @@
@------------------------------------------------------------------------------
+@ ROR
+ at ------------------------------------------------------------------------------
+ ror r2, r4, #31
+ ror r2, r4, #1
+ ror r2, r4, #0
+
+@ CHECK: ror r2, r4, #31 @ encoding: [0xe4,0x2f,0xa0,0xe1]
+@ CHECK: ror r2, r4, #1 @ encoding: [0xe4,0x20,0xa0,0xe1]
+@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
+
+
+ at ------------------------------------------------------------------------------
@ RSB
@------------------------------------------------------------------------------
rsb r4, r5, #0xf000
Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=144301&r1=144300&r2=144301&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Thu Nov 10 13:18:01 2011
@@ -24,13 +24,9 @@
@ Out of range immediates for ASR instruction.
asrs r2, r3, #33
- asrs r2, r3, #0
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: asrs r2, r3, #33
@ CHECK-ERRORS: ^
-@ CHECK-ERRORS: error: invalid operand for instruction
-@ CHECK-ERRORS: asrs r2, r3, #0
-@ CHECK-ERRORS: ^
@ Out of range immediates for BKPT instruction.
bkpt #256
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