[llvm-commits] [llvm] r143996 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/avx-basic.ll test/CodeGen/X86/sse2-blend.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/vec_return.ll test/CodeGen/X86/vec_zero.ll test/CodeGen/X86/vec_zero_cse.ll test/CodeGen/X86/xor.ll
Jakob Stoklund Olesen
stoklund at 2pi.dk
Mon Nov 7 11:15:59 PST 2011
Author: stoklund
Date: Mon Nov 7 13:15:58 2011
New Revision: 143996
URL: http://llvm.org/viewvc/llvm-project?rev=143996&view=rev
Log:
Expand V_SET0 to xorps by default.
The xorps instruction is smaller than pxor, so prefer that encoding.
The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/test/CodeGen/X86/avx-basic.ll
llvm/trunk/test/CodeGen/X86/sse2-blend.ll
llvm/trunk/test/CodeGen/X86/sse2.ll
llvm/trunk/test/CodeGen/X86/vec_return.ll
llvm/trunk/test/CodeGen/X86/vec_zero.ll
llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll
llvm/trunk/test/CodeGen/X86/xor.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Nov 7 13:15:58 2011
@@ -2420,7 +2420,7 @@
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
switch (MI->getOpcode()) {
case X86::V_SET0:
- return Expand2AddrUndef(MI, get(HasAVX ? X86::VPXORrr : X86::PXORrr));
+ return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
case X86::TEST8ri_NOREX:
MI->setDesc(get(X86::TEST8ri));
return true;
Modified: llvm/trunk/test/CodeGen/X86/avx-basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-basic.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-basic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-basic.ll Mon Nov 7 13:15:58 2011
@@ -6,7 +6,7 @@
define void @zero128() nounwind ssp {
entry:
- ; CHECK: vpxor
+ ; CHECK: vxorps
; CHECK: vmovaps
store <4 x float> zeroinitializer, <4 x float>* @z, align 16
ret void
Modified: llvm/trunk/test/CodeGen/X86/sse2-blend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-blend.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-blend.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-blend.ll Mon Nov 7 13:15:58 2011
@@ -26,8 +26,10 @@
ret void
}
+; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the
+; mixed domains here.
; CHECK: vsel_i64
-; CHECK: pxor
+; CHECK: xorps
; CHECK: pand
; CHECK: andnps
; CHECK: orps
@@ -41,8 +43,10 @@
ret void
}
+; FIXME: The -mattr=+sse2,-sse41 disable the ExecutionDepsFix pass causing the
+; mixed domains here.
; CHECK: vsel_double
-; CHECK: pxor
+; CHECK: xorps
; CHECK: pand
; CHECK: andnps
; CHECK: orps
Modified: llvm/trunk/test/CodeGen/X86/sse2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2.ll Mon Nov 7 13:15:58 2011
@@ -98,7 +98,7 @@
ret void
; CHECK: test7:
-; CHECK: pxor %xmm0, %xmm0
+; CHECK: xorps %xmm0, %xmm0
; CHECK: movaps %xmm0, 0
}
Modified: llvm/trunk/test/CodeGen/X86/vec_return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_return.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_return.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_return.ll Mon Nov 7 13:15:58 2011
@@ -1,12 +1,17 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
-; RUN: grep pxor %t | count 1
-; RUN: grep movaps %t | count 1
-; RUN: not grep shuf %t
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; Without any typed operations, always use the smaller xorps.
+; CHECK: test
+; CHECK: xorps
define <2 x double> @test() {
ret <2 x double> zeroinitializer
}
+; Prefer a constant pool load here.
+; CHECK: test2
+; CHECK-NOT: shuf
+; CHECK: movaps LCP
+; CHECK-NEXT: ret
define <4 x i32> @test2() nounwind {
ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 >
}
Modified: llvm/trunk/test/CodeGen/X86/vec_zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_zero.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_zero.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_zero.ll Mon Nov 7 13:15:58 2011
@@ -1,5 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; CHECK: foo
; CHECK: xorps
define void @foo(<4 x float>* %P) {
%T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
@@ -8,6 +9,7 @@
ret void
}
+; CHECK: bar
; CHECK: pxor
define void @bar(<4 x i32>* %P) {
%T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1]
@@ -16,3 +18,13 @@
ret void
}
+; Without any type hints from operations, we fall back to the smaller xorps.
+; The IR type <4 x i32> is ignored.
+; CHECK: untyped_zero
+; CHECK: xorps
+; CHECK: movaps
+define void @untyped_zero(<4 x i32>* %p) {
+entry:
+ store <4 x i32> zeroinitializer, <4 x i32>* %p, align 16
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_zero_cse.ll Mon Nov 7 13:15:58 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1
; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 1
; 64-bit stores here do not use MMX.
Modified: llvm/trunk/test/CodeGen/X86/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor.ll?rev=143996&r1=143995&r2=143996&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor.ll Mon Nov 7 13:15:58 2011
@@ -8,7 +8,7 @@
ret <4 x i32> %tmp
; X32: test1:
-; X32: pxor %xmm0, %xmm0
+; X32: xorps %xmm0, %xmm0
; X32: ret
}
More information about the llvm-commits
mailing list