[llvm-commits] [llvm] r143552 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

[Owen Anderson]

Author: resistor
Date: Wed Nov  2 12:41:23 2011
New Revision: 143552

URL: http://llvm.org/viewvc/llvm-project?rev=143552&view=rev
Log:
Register list operands are not allowed to contain only a single register.  Alternate encodings are used in that case.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=143552&r1=143551&r2=143552&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Nov  2 12:41:23 2011
@@ -1111,7 +1111,11 @@
   }
 
   // Empty register lists are not allowed.
-  if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
+  uint32_t popcnt = CountPopulation_32(Val);
+  if (popcnt == 0) return MCDisassembler::Fail;
+  // and one-register lists are unpredictable.
+  else if (popcnt == 1) Check(S, MCDisassembler::SoftFail);
+
   for (unsigned i = 0; i < 16; ++i) {
     if (Val & (1 << i)) {
       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))