[llvm-commits] [llvm] r143220 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

[Owen Anderson]

Author: resistor
Date: Fri Oct 28 15:43:24 2011
New Revision: 143220

URL: http://llvm.org/viewvc/llvm-project?rev=143220&view=rev
Log:
Specify that the high bit of the alignment field is fixed to 0 on these instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=143220&r1=143219&r2=143220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Oct 28 15:43:24 2011
@@ -389,7 +389,7 @@
                      "vld1", Dt, "$Vd, $Rn!",
                      "$Rn.addr = $wb", []> {
     let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
-    let Inst{5-4} = Rn{5-4};
+    let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
     let AsmMatchConverter = "cvtVLDwbFixed";
   }
@@ -397,7 +397,7 @@
                         (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
                         "vld1", Dt, "$Vd, $Rn, $Rm",
                         "$Rn.addr = $wb", []> {
-    let Inst{5-4} = Rn{5-4};
+    let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
     let AsmMatchConverter = "cvtVLDwbRegister";
   }