[llvm-commits] [llvm] r143200 - /llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

[Jim Grosbach]

Author: grosbach
Date: Fri Oct 28 11:43:40 2011
New Revision: 143200

URL: http://llvm.org/viewvc/llvm-project?rev=143200&view=rev
Log:
Allow register classes to match a containing class in InstAliases.

If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

Modified:
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=143200&r1=143199&r2=143200&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Fri Oct 28 11:43:40 2011
@@ -423,6 +423,15 @@
     return true;
   }
 
+  // For register operands, the source register class can be a subclass
+  // of the instruction register class, not just an exact match.
+  if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
+    if (!InstOpRec->isSubClassOf("RegisterClass"))
+      return false;
+    return T.getRegisterClass(InstOpRec)
+              .hasSubClass(&T.getRegisterClass(ADI->getDef()));
+  }
+
   // Handle explicit registers.
   if (ADI && ADI->getDef()->isSubClassOf("Register")) {
     if (InstOpRec->isSubClassOf("OptionalDefOperand")) {