[llvm-commits] [llvm] r143164 - in /llvm/trunk: ./ autoconf/ cmake/ docs/ include/llvm/ include/llvm/ADT/ lib/Support/ lib/Target/Alpha/ projects/sample/ projects/sample/autoconf/ test/CodeGen/Alpha/ tools/bugpoint/ utils/lit/lit/ExampleTests/LLVM.InTree/test/ utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/
Dan Gohman
gohman at apple.com
Thu Oct 27 15:56:33 PDT 2011
Author: djg
Date: Thu Oct 27 17:56:32 2011
New Revision: 143164
URL: http://llvm.org/viewvc/llvm-project?rev=143164&view=rev
Log:
Remove the Alpha backend.
Removed:
llvm/trunk/include/llvm/IntrinsicsAlpha.td
llvm/trunk/lib/Target/Alpha/
llvm/trunk/test/CodeGen/Alpha/
Modified:
llvm/trunk/CMakeLists.txt
llvm/trunk/autoconf/configure.ac
llvm/trunk/cmake/config-ix.cmake
llvm/trunk/configure
llvm/trunk/docs/CMake.html
llvm/trunk/docs/CodeGenerator.html
llvm/trunk/docs/CompilerWriterInfo.html
llvm/trunk/docs/UsingLibraries.html
llvm/trunk/include/llvm/ADT/Triple.h
llvm/trunk/include/llvm/Intrinsics.td
llvm/trunk/lib/Support/Triple.cpp
llvm/trunk/projects/sample/autoconf/configure.ac
llvm/trunk/projects/sample/configure
llvm/trunk/tools/bugpoint/ToolRunner.cpp
llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
Modified: llvm/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/CMakeLists.txt (original)
+++ llvm/trunk/CMakeLists.txt Thu Oct 27 17:56:32 2011
@@ -64,7 +64,6 @@
endif()
set(LLVM_ALL_TARGETS
- Alpha
ARM
CBackend
CellSPU
Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Thu Oct 27 17:56:32 2011
@@ -352,7 +352,6 @@
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
- alpha*-*) llvm_cv_target_arch="Alpha" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -487,7 +486,6 @@
Sparc) AC_SUBST(TARGET_HAS_JIT,0) ;;
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
- Alpha) AC_SUBST(TARGET_HAS_JIT,0) ;;
ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -603,21 +601,20 @@
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
- host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ host, x86, x86_64, sparc, powerpc, arm, mips, spu,
xcore, msp430, ptx, cbe, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -632,7 +629,6 @@
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
Modified: llvm/trunk/cmake/config-ix.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/cmake/config-ix.cmake (original)
+++ llvm/trunk/cmake/config-ix.cmake Thu Oct 27 17:56:32 2011
@@ -309,8 +309,6 @@
set(LLVM_NATIVE_ARCH Sparc)
elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
set(LLVM_NATIVE_ARCH PowerPC)
-elseif (LLVM_NATIVE_ARCH MATCHES "alpha")
- set(LLVM_NATIVE_ARCH Alpha)
elseif (LLVM_NATIVE_ARCH MATCHES "arm")
set(LLVM_NATIVE_ARCH ARM)
elseif (LLVM_NATIVE_ARCH MATCHES "mips")
Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Thu Oct 27 17:56:32 2011
@@ -1415,7 +1415,7 @@
(default is YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
- x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ x86_64, sparc, powerpc, arm, mips, spu,
xcore, msp430, ptx, cbe, and cpp (default=all)
--enable-cbe-printf-a Enable C Backend output with hex floating point via
%a (default is YES)
@@ -3874,7 +3874,6 @@
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
- alpha*-*) llvm_cv_target_arch="Alpha" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -5072,8 +5071,6 @@
;;
x86_64) TARGET_HAS_JIT=1
;;
- Alpha) TARGET_HAS_JIT=0
- ;;
ARM) TARGET_HAS_JIT=1
;;
Mips) TARGET_HAS_JIT=1
@@ -5270,14 +5267,13 @@
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5292,7 +5288,6 @@
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
Modified: llvm/trunk/docs/CMake.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CMake.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/CMake.html (original)
+++ llvm/trunk/docs/CMake.html Thu Oct 27 17:56:32 2011
@@ -249,7 +249,7 @@
<dd>Semicolon-separated list of targets to build, or <i>all</i> for
building all targets. Case-sensitive. For Visual C++ defaults
to <i>X86</i>. On the other cases defaults to <i>all</i>. Example:
- <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha"</i>.</dd>
+ <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</i>.</dd>
<dt><b>LLVM_BUILD_TOOLS</b>:BOOL</dt>
<dd>Build LLVM tools. Defaults to ON. Targets for building each tool
Modified: llvm/trunk/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.html (original)
+++ llvm/trunk/docs/CodeGenerator.html Thu Oct 27 17:56:32 2011
@@ -2208,7 +2208,6 @@
<tr>
<th>Feature</th>
<th>ARM</th>
- <th>Alpha</th>
<th>CellSPU</th>
<th>MBlaze</th>
<th>MSP430</th>
@@ -2223,7 +2222,6 @@
<tr>
<td><a href="#feat_reliable">is generally reliable</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2238,7 +2236,6 @@
<tr>
<td><a href="#feat_asmparser">assembly parser</a></td>
<td class="no"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2253,7 +2250,6 @@
<tr>
<td><a href="#feat_disassembler">disassembler</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2268,7 +2264,6 @@
<tr>
<td><a href="#feat_inlineasm">inline asm</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2283,7 +2278,6 @@
<tr>
<td><a href="#feat_jit">jit</a></td>
<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2298,7 +2292,6 @@
<tr>
<td><a href="#feat_objectwrite">.o file writing</a></td>
<td class="no"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2313,7 +2306,6 @@
<tr>
<td><a href="#feat_tailcall">tail calls</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
Modified: llvm/trunk/docs/CompilerWriterInfo.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerWriterInfo.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/CompilerWriterInfo.html (original)
+++ llvm/trunk/docs/CompilerWriterInfo.html Thu Oct 27 17:56:32 2011
@@ -21,7 +21,6 @@
<ol>
<li><a href="#hw">Hardware</a>
<ol>
- <li><a href="#alpha">Alpha</a></li>
<li><a href="#arm">ARM</a></li>
<li><a href="#ia64">Itanium</a></li>
<li><a href="#mips">MIPS</a></li>
@@ -49,17 +48,6 @@
<div>
<!-- ======================================================================= -->
-<h3><a name="alpha">Alpha</a></h3>
-
-<div>
-<ul>
-<li><a
-href="http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html">Alpha manuals</a>
-</li>
-</ul>
-</div>
-
-<!-- ======================================================================= -->
<h3><a name="arm">ARM</a></h3>
<div>
Modified: llvm/trunk/docs/UsingLibraries.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/UsingLibraries.html?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/docs/UsingLibraries.html (original)
+++ llvm/trunk/docs/UsingLibraries.html Thu Oct 27 17:56:32 2011
@@ -126,8 +126,6 @@
<td>Aggressive instruction selector for directed acyclic graphs</td></tr>
<tr><th colspan="3">Target Libraries</th></tr>
- <tr><td>LLVMAlpha</td><td><tt>.o</tt></td>
- <td>Code generation for Alpha architecture</td></tr>
<tr><td>LLVMARM</td><td><tt>.o</tt></td>
<td>Code generation for ARM architecture</td></tr>
<tr><td>LLVMCBackend</td><td><tt>.o</tt></td>
@@ -333,14 +331,6 @@
<li>libLLVMSystem.a</li>
<li>libLLVMTarget.a</li>
</ul></dd>
- <dt><b>LLVMAlpha.o</b></dt><dd><ul>
- <li>libLLVMCodeGen.a</li>
- <li>libLLVMCore.a</li>
- <li>libLLVMSelectionDAG.a</li>
- <li>libLLVMSupport.a</li>
- <li>libLLVMSystem.a</li>
- <li>libLLVMTarget.a</li>
- </ul></dd>
<dt><b>LLVMCBackend.o</b></dt><dd><ul>
<li>libLLVMAnalysis.a</li>
<li>libLLVMCodeGen.a</li>
Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Thu Oct 27 17:56:32 2011
@@ -43,7 +43,6 @@
enum ArchType {
UnknownArch,
- alpha, // Alpha: alpha
arm, // ARM; arm, armv.*, xscale
cellspu, // CellSPU: spu, cellspu
mips, // MIPS: mips, mipsallegrex
Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Thu Oct 27 17:56:32 2011
@@ -443,6 +443,5 @@
include "llvm/IntrinsicsX86.td"
include "llvm/IntrinsicsARM.td"
include "llvm/IntrinsicsCellSPU.td"
-include "llvm/IntrinsicsAlpha.td"
include "llvm/IntrinsicsXCore.td"
include "llvm/IntrinsicsPTX.td"
Removed: llvm/trunk/include/llvm/IntrinsicsAlpha.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsAlpha.td?rev=143163&view=auto
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsAlpha.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsAlpha.td (removed)
@@ -1,18 +0,0 @@
-//===- IntrinsicsAlpha.td - Defines Alpha intrinsics -------*- tablegen -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines all of the Alpha-specific intrinsics.
-//
-//===----------------------------------------------------------------------===//
-
-
-let TargetPrefix = "alpha" in { // All intrinsics start with "llvm.alpha.".
- def int_alpha_umulh : GCCBuiltin<"__builtin_alpha_umulh">,
- Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
-}
Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Thu Oct 27 17:56:32 2011
@@ -18,7 +18,6 @@
case InvalidArch: return "<invalid>";
case UnknownArch: return "unknown";
- case alpha: return "alpha";
case arm: return "arm";
case cellspu: return "cellspu";
case mips: return "mips";
@@ -50,8 +49,6 @@
default:
return 0;
- case alpha: return "alpha";
-
case arm:
case thumb: return "arm";
@@ -131,8 +128,6 @@
}
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
- if (Name == "alpha")
- return alpha;
if (Name == "arm")
return arm;
if (Name == "cellspu")
@@ -286,8 +281,6 @@
else if (ArchName == "thumb" ||
ArchName.startswith("thumbv"))
return thumb;
- else if (ArchName.startswith("alpha"))
- return alpha;
else if (ArchName == "spu" || ArchName == "cellspu")
return cellspu;
else if (ArchName == "msp430")
Modified: llvm/trunk/projects/sample/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/autoconf/configure.ac?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/projects/sample/autoconf/configure.ac (original)
+++ llvm/trunk/projects/sample/autoconf/configure.ac Thu Oct 27 17:56:32 2011
@@ -296,7 +296,6 @@
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
- alpha*-*) llvm_cv_target_arch="Alpha" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -431,7 +430,6 @@
Sparc) AC_SUBST(TARGET_HAS_JIT,0) ;;
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
- Alpha) AC_SUBST(TARGET_HAS_JIT,0) ;;
ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -547,21 +545,20 @@
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
- host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ host, x86, x86_64, sparc, powerpc, arm, mips, spu,
xcore, msp430, ptx, cbe, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -576,7 +573,6 @@
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
Modified: llvm/trunk/projects/sample/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/sample/configure?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/projects/sample/configure (original)
+++ llvm/trunk/projects/sample/configure Thu Oct 27 17:56:32 2011
@@ -1401,7 +1401,7 @@
(default is YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
- x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ x86_64, sparc, powerpc, arm, mips, spu,
xcore, msp430, ptx, cbe, and cpp
(default=all)
--enable-cbe-printf-a Enable C Backend output with hex floating point via
@@ -3840,7 +3840,6 @@
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
- alpha*-*) llvm_cv_target_arch="Alpha" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -5038,8 +5037,6 @@
;;
x86_64) TARGET_HAS_JIT=1
;;
- Alpha) TARGET_HAS_JIT=0
- ;;
ARM) TARGET_HAS_JIT=1
;;
Mips) TARGET_HAS_JIT=1
@@ -5236,14 +5233,13 @@
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5258,7 +5254,6 @@
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original)
+++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Thu Oct 27 17:56:32 2011
@@ -920,8 +920,7 @@
} else
GCCArgs.push_back("-shared"); // `-shared' for Linux/X86, maybe others
- if ((TargetTriple.getArch() == Triple::alpha) ||
- (TargetTriple.getArch() == Triple::x86_64))
+ if (TargetTriple.getArch() == Triple::x86_64)
GCCArgs.push_back("-fPIC"); // Requires shared objs to contain PIC
if (TargetTriple.getArch() == Triple::sparc)
Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp Thu Oct 27 17:56:32 2011
@@ -2,7 +2,7 @@
# Do not edit here. If you wish to override these values
# edit the last section
set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
set srcroot "/Volumes/Data/ddunbar/llvm"
set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
set srcdir "/Volumes/Data/ddunbar/llvm/test"
Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp?rev=143164&r1=143163&r2=143164&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp Thu Oct 27 17:56:32 2011
@@ -2,7 +2,7 @@
# Do not edit here. If you wish to override these values
# edit the last section
set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin CBackend MSIL CppBackend"
set srcroot "/Volumes/Data/ddunbar/llvm"
set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
set srcdir "/Volumes/Data/ddunbar/llvm/test"
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