[llvm-commits] [llvm] r142741 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86BaseInfo.h lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrFormats.td lib/Target/X86/X86InstrShiftRotate.td test/MC/Disassembler/X86/simple-tests.txt test/MC/Disassembler/X86/x86-32.txt test/MC/X86/x86_64-bmi-encoding.s utils/TableGen/X86RecognizableInstr.cpp
Craig Topper
craig.topper at gmail.com
Sun Oct 23 00:34:00 PDT 2011
Author: ctopper
Date: Sun Oct 23 02:34:00 2011
New Revision: 142741
URL: http://llvm.org/viewvc/llvm-project?rev=142741&view=rev
Log:
Add X86 RORX instruction
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
llvm/trunk/test/MC/X86/x86_64-bmi-encoding.s
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Sun Oct 23 02:34:00 2011
@@ -301,6 +301,9 @@
// T8XS - Prefix before and after 0x0F. Combination of T8 and XS.
T8XS = 18 << Op0Shift,
+ // TAXD - Prefix before and after 0x0F. Combination of TA and XD.
+ TAXD = 19 << Op0Shift,
+
//===------------------------------------------------------------------===//
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
// They are used to specify GPRs and SSE registers, 64-bit operand size,
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Sun Oct 23 02:34:00 2011
@@ -472,6 +472,10 @@
VEX_PP = 0x3;
VEX_5M = 0x2;
break;
+ case X86II::TAXD: // F2 0F 3A
+ VEX_PP = 0x3;
+ VEX_5M = 0x3;
+ break;
case X86II::XS: // F3 0F
VEX_PP = 0x2;
break;
@@ -802,6 +806,10 @@
EmitByte(0xF2, CurByte, OS);
Need0FPrefix = true;
break;
+ case X86II::TAXD: // F2 0F 3A
+ EmitByte(0xF2, CurByte, OS);
+ Need0FPrefix = true;
+ break;
case X86II::XS: // F3 0F
EmitByte(0xF3, CurByte, OS);
Need0FPrefix = true;
@@ -838,6 +846,7 @@
case X86II::T8: // 0F 38
EmitByte(0x38, CurByte, OS);
break;
+ case X86II::TAXD: // F2 0F 3A
case X86II::TA: // 0F 3A
EmitByte(0x3A, CurByte, OS);
break;
Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Sun Oct 23 02:34:00 2011
@@ -656,6 +656,7 @@
Need0FPrefix = true;
break;
case X86II::T8XD: // F2 0F 38
+ case X86II::TAXD: // F2 0F 3A
case X86II::XD: // F2 0F
MCE.emitByte(0xF2);
Need0FPrefix = true;
@@ -686,6 +687,7 @@
case X86II::T8: // 0F 38
MCE.emitByte(0x38);
break;
+ case X86II::TAXD: // F2 0F 38
case X86II::TA: // 0F 3A
MCE.emitByte(0x3A);
break;
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Sun Oct 23 02:34:00 2011
@@ -109,6 +109,7 @@
class A7 { bits<5> Prefix = 16; }
class T8XD { bits<5> Prefix = 17; }
class T8XS { bits<5> Prefix = 18; }
+class TAXD { bits<5> Prefix = 19; }
class VEX { bit hasVEXPrefix = 1; }
class VEX_W { bit hasVEX_WPrefix = 1; }
class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Sun Oct 23 02:34:00 2011
@@ -744,3 +744,24 @@
} // Defs = [EFLAGS]
+let Predicates = [HasBMI2], neverHasSideEffects = 1 in {
+ def RORX32ri : Ii8<0xF0, MRMSrcReg, (outs GR32:$dst),
+ (ins GR32:$src1, i8imm:$src2),
+ "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+ TAXD, VEX;
+ let mayLoad = 1 in
+ def RORX32mi : Ii8<0xF0, MRMSrcMem, (outs GR32:$dst),
+ (ins i32mem:$src1, i8imm:$src2),
+ "rorx{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+ TAXD, VEX;
+
+ def RORX64ri : Ii8<0xF0, MRMSrcReg, (outs GR64:$dst),
+ (ins GR64:$src1, i8imm:$src2),
+ "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+ TAXD, VEX, VEX_W;
+ let mayLoad = 1 in
+ def RORX64mi : Ii8<0xF0, MRMSrcMem, (outs GR64:$dst),
+ (ins i64mem:$src1, i8imm:$src2),
+ "rorx{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+ TAXD, VEX, VEX_W;
+}
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Oct 23 02:34:00 2011
@@ -599,3 +599,15 @@
# CHECK: mulxq (%rax), %r11, %r10
0xc4 0x62 0xa3 0xf6 0x10
+
+# CHECK: rorxl $1, %r12d, %r10d
+0xc4 0x43 0x7b 0xf0 0xd4 0x01
+
+# CHECK: rorxl $31, (%rax), %r10d
+0xc4 0x63 0x7b 0xf0 0x10 0x1f
+
+# CHECK: rorxq $1, %r12, %r10
+0xc4 0x43 0xfb 0xf0 0xd4 0x01
+
+# CHECK: rorxq $63, (%rax), %r10
+0xc4 0x63 0xfb 0xf0 0x10 0x3f
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Sun Oct 23 02:34:00 2011
@@ -543,3 +543,9 @@
# CHECK: mulxl (%eax), %ecx, %edx
0xc4 0xe2 0xf3 0xf6 0x10
+
+# CHECK: rorxl $1, %esp, %edx
+0xc4 0xe3 0x7b 0xf0 0xd4 0x01
+
+# CHECK: rorxl $31, (%eax), %edx
+0xc4 0xe3 0x7b 0xf0 0x10 0x1f
Modified: llvm/trunk/test/MC/X86/x86_64-bmi-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-bmi-encoding.s?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-bmi-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-bmi-encoding.s Sun Oct 23 02:34:00 2011
@@ -119,3 +119,35 @@
// CHECK: pdepq (%rax), %r11, %r10
// CHECK: encoding: [0xc4,0x62,0xa3,0xf5,0x10]
pdepq (%rax), %r11, %r10
+
+// CHECK: mulxl %r12d, %r11d, %r10d
+// CHECK: encoding: [0xc4,0x42,0x23,0xf6,0xd4]
+ mulxl %r12d, %r11d, %r10d
+
+// CHECK: mulxl (%rax), %r11d, %r10d
+// CHECK: encoding: [0xc4,0x62,0x23,0xf6,0x10]
+ mulxl (%rax), %r11d, %r10d
+
+// CHECK: mulxq %r12, %r11, %r10
+// CHECK: encoding: [0xc4,0x42,0xa3,0xf6,0xd4]
+ mulxq %r12, %r11, %r10
+
+// CHECK: mulxq (%rax), %r11, %r10
+// CHECK: encoding: [0xc4,0x62,0xa3,0xf6,0x10]
+ mulxq (%rax), %r11, %r10
+
+// CHECK: rorxl $10, %r12d, %r10d
+// CHECK: encoding: [0xc4,0x43,0x7b,0xf0,0xd4,0x0a]
+ rorxl $10, %r12d, %r10d
+
+// CHECK: rorxl $31, (%rax), %r10d
+// CHECK: encoding: [0xc4,0x63,0x7b,0xf0,0x10,0x1f]
+ rorxl $31, (%rax), %r10d
+
+// CHECK: rorxq $1, %r12, %r10
+// CHECK: encoding: [0xc4,0x43,0xfb,0xf0,0xd4,0x01]
+ rorxq $1, %r12, %r10
+
+// CHECK: rorxq $63, (%rax), %r10
+// CHECK: encoding: [0xc4,0x63,0xfb,0xf0,0x10,0x3f]
+ rorxq $63, (%rax), %r10
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=142741&r1=142740&r2=142741&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Oct 23 02:34:00 2011
@@ -68,7 +68,7 @@
DC = 7, DD = 8, DE = 9, DF = 10,
XD = 11, XS = 12,
T8 = 13, P_TA = 14,
- A6 = 15, A7 = 16, T8XD = 17, T8XS = 18
+ A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
};
}
@@ -296,20 +296,23 @@
else if (HasVEX_LPrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_VEX_L_XS;
- else if (HasVEX_LPrefix &&
- (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
+ else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
+ Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD))
insnContext = IC_VEX_L_XD;
else if (HasVEX_WPrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_VEX_W_XS;
- else if (HasVEX_WPrefix &&
- (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
+ else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
+ Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD))
insnContext = IC_VEX_W_XD;
else if (HasVEX_WPrefix)
insnContext = IC_VEX_W;
else if (HasVEX_LPrefix)
insnContext = IC_VEX_L;
- else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD)
+ else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD)
insnContext = IC_VEX_XD;
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = IC_VEX_XS;
@@ -318,8 +321,9 @@
} else if (Is64Bit || HasREX_WPrefix) {
if (HasREX_WPrefix && HasOpSizePrefix)
insnContext = IC_64BIT_REXW_OPSIZE;
- else if (HasOpSizePrefix &&
- (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
+ else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
+ Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD))
insnContext = IC_64BIT_XD_OPSIZE;
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
@@ -329,10 +333,12 @@
else if (HasREX_WPrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_64BIT_REXW_XS;
- else if (HasREX_WPrefix &&
- (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
+ else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
+ Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD))
insnContext = IC_64BIT_REXW_XD;
- else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD)
+ else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD)
insnContext = IC_64BIT_XD;
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = IC_64BIT_XS;
@@ -341,15 +347,17 @@
else
insnContext = IC_64BIT;
} else {
- if (HasOpSizePrefix &&
- (Prefix == X86Local::XD || Prefix == X86Local::T8XD))
+ if (HasOpSizePrefix && (Prefix == X86Local::XD ||
+ Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD))
insnContext = IC_XD_OPSIZE;
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_XS_OPSIZE;
else if (HasOpSizePrefix)
insnContext = IC_OPSIZE;
- else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD)
+ else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
+ Prefix == X86Local::TAXD)
insnContext = IC_XD;
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
Prefix == X86Local::REP)
@@ -908,6 +916,7 @@
opcodeToSet = Opcode;
break;
case X86Local::P_TA:
+ case X86Local::TAXD:
opcodeType = THREEBYTE_3A;
if (needsModRMForDecode(Form))
filter = new ModFilter(isRegFormat(Form));
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