[llvm-commits] [llvm] r142618 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Owen Anderson]

Author: resistor
Date: Thu Oct 20 16:24:38 2011
New Revision: 142618

URL: http://llvm.org/viewvc/llvm-project?rev=142618&view=rev
Log:
Separate out ARM MSR instructions into M-class versions and AR-class versions.  This fixes some roundtripping failures.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=142618&r1=142617&r2=142618&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Oct 20 16:24:38 2011
@@ -4562,8 +4562,13 @@
 // same and the assembly parser has no way to distinguish between them. The mask
 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
 // the mask with the fields to be accessed in the special register.
-def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
-              "msr", "\t$mask, $Rn", []> {
+//
+// NOTE: There are separate versions of these instructions for M-class versus
+// AR-class processors.  M-class processors can accept a wider range of
+// mask values than AR-class processors can.
+def MSRm : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
+              "msr", "\t$mask, $Rn", []>,
+          Requires<[IsMClass]> {
   bits<5> mask;
   bits<4> Rn;
 
@@ -4576,8 +4581,9 @@
   let Inst{3-0} = Rn;
 }
 
-def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask,  so_imm:$a), NoItinerary,
-               "msr", "\t$mask, $a", []> {
+def MSRmi : ABI<0b0011, (outs), (ins msr_mask:$mask,  so_imm:$a), NoItinerary,
+               "msr", "\t$mask, $a", []>,
+           Requires<[IsMClass]> {
   bits<5> mask;
   bits<12> a;
 
@@ -4589,6 +4595,38 @@
   let Inst{11-0} = a;
 }
 
+def MSRar : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
+              "msr", "\t$mask, $Rn", []>,
+          Requires<[IsARClass]> {
+  bits<5> mask;
+  bits<4> Rn;
+
+  let Inst{23} = 0;
+  let Inst{22} = 0;
+  let Inst{21-20} = 0b10;
+  let Inst{19-18} = mask{3-2};
+  let Inst{17-16} = 0b00;
+  let Inst{15-12} = 0b1111;
+  let Inst{11-4} = 0b00000000;
+  let Inst{3-0} = Rn;
+}
+
+def MSRari : ABI<0b0011, (outs), (ins msr_mask:$mask,  so_imm:$a), NoItinerary,
+               "msr", "\t$mask, $a", []>,
+           Requires<[IsARClass]> {
+  bits<5> mask;
+  bits<12> a;
+
+  let Inst{23} = 0;
+  let Inst{22} = 0;
+  let Inst{21-20} = 0b10;
+  let Inst{19-18} = mask{3-2};
+  let Inst{17-16} = 0b00;
+  let Inst{15-12} = 0b1111;
+  let Inst{11-0} = a;
+}
+
+
 //===----------------------------------------------------------------------===//
 // TLS Instructions
 //