[llvm-commits] [llvm] r142431 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Jim Grosbach]

Will it always be less than 65536 (the limit of the MOVi16 instruction)?

Either way, we should conditionally use the CMPri instruction for those (common, I'd expect) cases where the value does fit in the immediate for that instruction.

Also, do Thumb and Thumb2 have similar issues?

-Jim


On Oct 18, 2011, at 3:11 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Oct 18 17:11:18 2011
> New Revision: 142431
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142431&view=rev
> Log:
> The value we're comparing against may be too large for the ARM CMP
> instruction. Move the value into a register and then use that for the CMP.
> <rdar://problem/10305266>
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142431&r1=142430&r2=142431&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 17:11:18 2011
> @@ -5849,38 +5849,42 @@
>                    .addFrameIndex(FI)
>                    .addImm(4)
>                    .addMemOperand(FIMMOLd));
> -    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
> -                   .addReg(NewVReg1)
> +
> +    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
> +    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), NewVReg2)
>                    .addImm(LPadList.size()));
> +    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
> +                   .addReg(NewVReg1)
> +                   .addReg(NewVReg2));
>     BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
>       .addMBB(TrapBB)
>       .addImm(ARMCC::HI)
>       .addReg(ARM::CPSR);
> 
> -    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
> +    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
>     AddDefaultCC(
> -      AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2)
> +      AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
>                      .addReg(NewVReg1)
>                      .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
> -    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
> -    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3)
> +    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
> +    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
>                    .addJumpTableIndex(MJTI)
>                    .addImm(UId));
> 
>     MachineMemOperand *JTMMOLd =
>       MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
>                                MachineMemOperand::MOLoad, 4, 4);
> -    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
> +    unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
>     AddDefaultPred(
> -      BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4)
> -      .addReg(NewVReg2, RegState::Kill)
> -      .addReg(NewVReg3)
> +      BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
> +      .addReg(NewVReg3, RegState::Kill)
> +      .addReg(NewVReg4)
>       .addImm(0)
>       .addMemOperand(JTMMOLd));
> 
>     BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
> -      .addReg(NewVReg4, RegState::Kill)
> -      .addReg(NewVReg3)
> +      .addReg(NewVReg5, RegState::Kill)
> +      .addReg(NewVReg4)
>       .addJumpTableIndex(MJTI)
>       .addImm(UId);
>   }
> 
> 
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