[llvm-commits] [llvm] r142429 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Chad Rosier]

Hi Bill,
See inline comments below:

On Oct 18, 2011, at 2:55 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Oct 18 16:55:58 2011
> New Revision: 142429
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142429&view=rev
> Log:
> The immediate may be too large for the CMP instruction. Move it into a register
> and use that in the CMP.
> <rdar://problem/10305266>
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142429&r1=142428&r2=142429&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 16:55:58 2011
> @@ -5760,29 +5760,34 @@
>                    .addFrameIndex(FI)
>                    .addImm(4)
>                    .addMemOperand(FIMMOLd));
> -    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
> -                   .addReg(NewVReg1)
> +
> +    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
> +    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), NewVReg2)
>                    .addImm(LPadList.size()));
> +
> +    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
> +                   .addReg(NewVReg1)
> +                   .addReg(NewVReg2));

Couldn't we check to see if the immediate is too large, then generate the mov only if necessary.  Something like:

if ((LPadList.size() & 0xff) == 0xff) {
    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
        .addReg(NewVReg1)
       .addImm(LPadList.size()));
} else {
    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), NewVReg2)
                   .addImm(LPadList.size()));
    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
                   .addReg(NewVReg1)
                   .addReg(NewVReg2));
}

 Chad

>     BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
>       .addMBB(TrapBB)
>       .addImm(ARMCC::HI)
>       .addReg(ARM::CPSR);
> 
> -    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
> -    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2)
> +    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
> +    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
>                    .addJumpTableIndex(MJTI)
>                    .addImm(UId));
> 
> -    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
> +    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
>     AddDefaultCC(
>       AddDefaultPred(
> -        BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3)
> -        .addReg(NewVReg2, RegState::Kill)
> +        BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
> +        .addReg(NewVReg3, RegState::Kill)
>         .addReg(NewVReg1)
>         .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
> 
>     BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
> -      .addReg(NewVReg3, RegState::Kill)
> +      .addReg(NewVReg4, RegState::Kill)
>       .addReg(NewVReg1)
>       .addJumpTableIndex(MJTI)
>       .addImm(UId);
> 
> 
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