[llvm-commits] [llvm] r142371 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vmul.ll

[Bob Wilson]

I figured there must be such a function but couldn't find it....  Changed in r142395.  Thanks!

On Oct 18, 2011, at 11:08 AM, Eli Friedman wrote:

> On Tue, Oct 18, 2011 at 10:34 AM, Bob Wilson <bob.wilson at apple.com> wrote:
>> Author: bwilson
>> Date: Tue Oct 18 12:34:51 2011
>> New Revision: 142371
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=142371&view=rev
>> Log:
>> Fix incorrect check for sign-extended constant BUILD_VECTOR.
>> <rdar://problem/10298332>
>> 
>> Modified:
>>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>    llvm/trunk/test/CodeGen/ARM/vmul.ll
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142371&r1=142370&r2=142371&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 12:34:51 2011
>> @@ -4527,7 +4527,7 @@
>>       unsigned HalfSize = EltSize / 2;
>>       if (isSigned) {
>>         int64_t SExtVal = C->getSExtValue();
>> -        if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
>> +        if (SExtVal != SExtVal << (64 - HalfSize) >> (64 - HalfSize))
>>           return false;
> 
> isIntN from MathExtras.h would make this a bit clearer.
> 
> -Eli
> 
>>       } else {
>>         if ((C->getZExtValue() >> HalfSize) != 0)
>> 
>> Modified: llvm/trunk/test/CodeGen/ARM/vmul.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=142371&r1=142370&r2=142371&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/vmul.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/vmul.ll Tue Oct 18 12:34:51 2011
>> @@ -514,3 +514,14 @@
>>   store <8 x i8> %10, <8 x i8>* %11, align 8
>>   ret void
>>  }
>> +
>> +; If one operand has a zero-extend and the other a sign-extend, vmull
>> +; cannot be used.
>> +define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
>> +; CHECK: vmullWithInconsistentExtensions
>> +; CHECK-NOT: vmull.s8
>> +  %1 = sext <8 x i8> %vec to <8 x i16>
>> +  %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
>> +  %3 = extractelement <8 x i16> %2, i32 0
>> +  ret i16 %3
>> +}
>> 
>> 
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