[llvm-commits] [llvm] r142303 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neont2-mov-encoding.s utils/TableGen/EDEmitter.cpp

Jim Grosbach grosbach at apple.com
Mon Oct 17 16:09:09 PDT 2011


Author: grosbach
Date: Mon Oct 17 18:09:09 2011
New Revision: 142303

URL: http://llvm.org/viewvc/llvm-project?rev=142303&view=rev
Log:
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/neont2-mov-encoding.s
    llvm/trunk/utils/TableGen/EDEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142303&r1=142302&r2=142303&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Oct 17 18:09:09 2011
@@ -24,6 +24,11 @@
   let PrintMethod = "printNEONModImmOperand";
   let ParserMatchClass = nImmSplatI8AsmOperand;
 }
+def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
+def nImmSplatI16 : Operand<i32> {
+  let PrintMethod = "printNEONModImmOperand";
+  let ParserMatchClass = nImmSplatI16AsmOperand;
+}
 
 def VectorIndex8Operand  : AsmOperandClass { let Name = "VectorIndex8"; }
 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
@@ -3743,7 +3748,7 @@
                       v4i32, v4i32, or, 1>;
 
 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
-                          (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
+                          (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
                           IIC_VMOVImm,
                           "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
                           [(set DPR:$Vd,
@@ -3761,7 +3766,7 @@
 }
 
 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
-                          (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
+                          (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
                           IIC_VMOVImm,
                           "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
                           [(set QPR:$Vd,
@@ -3792,7 +3797,7 @@
                                                  (vnotq QPR:$Vm))))]>;
 
 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
-                          (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
+                          (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
                           IIC_VMOVImm,
                           "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
                           [(set DPR:$Vd,
@@ -3810,7 +3815,7 @@
 }
 
 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
-                          (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
+                          (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
                           IIC_VMOVImm,
                           "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
                           [(set QPR:$Vd,
@@ -3844,14 +3849,14 @@
 let isReMaterializable = 1 in {
 
 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
-                         (ins nModImm:$SIMM), IIC_VMOVImm,
+                         (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$Vd, $SIMM", "",
                          [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
   let Inst{9} = SIMM{9};
 }
 
 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
-                         (ins nModImm:$SIMM), IIC_VMOVImm,
+                         (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$Vd, $SIMM", "",
                          [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
   let Inst{9} = SIMM{9};
@@ -4329,14 +4334,14 @@
                          [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
 
 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
-                         (ins nModImm:$SIMM), IIC_VMOVImm,
+                         (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
                          "vmov", "i16", "$Vd, $SIMM", "",
                          [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
   let Inst{9} = SIMM{9};
 }
 
 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
-                         (ins nModImm:$SIMM), IIC_VMOVImm,
+                         (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
                          "vmov", "i16", "$Vd, $SIMM", "",
                          [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
  let Inst{9} = SIMM{9};

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=142303&r1=142302&r2=142303&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Oct 17 18:09:09 2011
@@ -924,6 +924,17 @@
     return Value >= 0 && Value < 256;
   }
 
+  bool isNEONi16splat() const {
+    if (Kind != k_Immediate)
+      return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    // Must be a constant.
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    // i16 value in the range [0,255] or [0x0100, 0xff00]
+    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
+  }
+
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     // Add as immediates when possible.  Null MCExpr = 0.
     if (Expr == 0)
@@ -1454,6 +1465,18 @@
     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
   }
 
+  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // The immediate encodes the type of constant as well as the value.
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Value = CE->getValue();
+    if (Value >= 256)
+      Value = (Value >> 8) | 0xa00;
+    else
+      Value |= 0x800;
+    Inst.addOperand(MCOperand::CreateImm(Value));
+  }
+
   virtual void print(raw_ostream &OS) const;
 
   static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {

Modified: llvm/trunk/test/MC/ARM/neont2-mov-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mov-encoding.s?rev=142303&r1=142302&r2=142303&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mov-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mov-encoding.s Mon Oct 17 18:09:09 2011
@@ -3,8 +3,8 @@
 .code 16
 
 	vmov.i8	d16, #0x8
-@	vmov.i16	d16, #0x10
-@	vmov.i16	d16, #0x1000
+	vmov.i16	d16, #0x10
+	vmov.i16	d16, #0x1000
 @	vmov.i32	d16, #0x20
 @	vmov.i32	d16, #0x2000
 @	vmov.i32	d16, #0x200000
@@ -14,8 +14,8 @@
 @	vmov.i64	d16, #0xFF0000FF0000FFFF
 
 @ CHECK: vmov.i8	d16, #0x8       @ encoding: [0xc0,0xef,0x18,0x0e]
-@ FIXME: vmov.i16	d16, #0x10      @ encoding: [0xc1,0xef,0x10,0x08]
-@ FIXME: vmov.i16	d16, #0x1000    @ encoding: [0xc1,0xef,0x10,0x0a]
+@ CHECK: vmov.i16	d16, #0x10      @ encoding: [0xc1,0xef,0x10,0x08]
+@ CHECK: vmov.i16	d16, #0x1000    @ encoding: [0xc1,0xef,0x10,0x0a]
 @ FIXME: vmov.i32	d16, #0x20      @ encoding: [0xc2,0xef,0x10,0x00]
 @ FIXME: vmov.i32	d16, #0x2000    @ encoding: [0xc2,0xef,0x10,0x02]
 @ FIXME: vmov.i32	d16, #0x200000  @ encoding: [0xc2,0xef,0x10,0x04]
@@ -26,8 +26,8 @@
 
 
 	vmov.i8	q8, #0x8
-@	vmov.i16	q8, #0x10
-@	vmov.i16	q8, #0x1000
+	vmov.i16	q8, #0x10
+	vmov.i16	q8, #0x1000
 @	vmov.i32	q8, #0x20
 @	vmov.i32	q8, #0x2000
 @	vmov.i32	q8, #0x200000
@@ -37,8 +37,8 @@
 @	vmov.i64	q8, #0xFF0000FF0000FFFF
 
 @ CHECK: vmov.i8	q8, #0x8        @ encoding: [0xc0,0xef,0x58,0x0e]
-@ FIXME: vmov.i16	q8, #0x10       @ encoding: [0xc1,0xef,0x50,0x08]
-@ FIXME: vmov.i16	q8, #0x1000     @ encoding: [0xc1,0xef,0x50,0x0a]
+@ CHECK: vmov.i16	q8, #0x10       @ encoding: [0xc1,0xef,0x50,0x08]
+@ CHECK: vmov.i16	q8, #0x1000     @ encoding: [0xc1,0xef,0x50,0x0a]
 @ FIXME: vmov.i32	q8, #0x20       @ encoding: [0xc2,0xef,0x50,0x00]
 @ FIXME: vmov.i32	q8, #0x2000     @ encoding: [0xc2,0xef,0x50,0x02]
 @ FIXME: vmov.i32	q8, #0x200000   @ encoding: [0xc2,0xef,0x50,0x04]
@@ -48,8 +48,8 @@
 @ FIXME: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0xc1,0xff,0x73,0x0e]
 
 
-@	vmvn.i16	d16, #0x10
-@	vmvn.i16	d16, #0x1000
+	vmvn.i16	d16, #0x10
+	vmvn.i16	d16, #0x1000
 @	vmvn.i32	d16, #0x20
 @	vmvn.i32	d16, #0x2000
 @	vmvn.i32	d16, #0x200000
@@ -57,8 +57,8 @@
 @	vmvn.i32	d16, #0x20FF
 @	vmvn.i32	d16, #0x20FFFF
 
-@ FIXME: vmvn.i16	d16, #0x10      @ encoding: [0xc1,0xef,0x30,0x08]
-@ FIXME: vmvn.i16	d16, #0x1000    @ encoding: [0xc1,0xef,0x30,0x0a]
+@ CHECK: vmvn.i16	d16, #0x10      @ encoding: [0xc1,0xef,0x30,0x08]
+@ CHECK: vmvn.i16	d16, #0x1000    @ encoding: [0xc1,0xef,0x30,0x0a]
 @ FIXME: vmvn.i32	d16, #0x20      @ encoding: [0xc2,0xef,0x30,0x00]
 @ FIXME: vmvn.i32	d16, #0x2000    @ encoding: [0xc2,0xef,0x30,0x02]
 @ FIXME: vmvn.i32	d16, #0x200000  @ encoding: [0xc2,0xef,0x30,0x04]

Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=142303&r1=142302&r2=142303&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Oct 17 18:09:09 2011
@@ -598,6 +598,7 @@
   IMM("imm1_32");
   IMM("nModImm");
   IMM("nImmSplatI8");
+  IMM("nImmSplatI16");
   IMM("imm0_7");
   IMM("imm0_15");
   IMM("imm0_255");





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