[llvm-commits] [llvm] r142105 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86BaseInfo.h lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp lib/Target/X86/X86InstrInfo.td test/MC/Disassembler/X86/simple-tests.txt test/MC/Disassembler/X86/x86-32.txt test/MC/X86/x86_64-bmi-encoding.s utils/TableGen/X86RecognizableInstr.cpp utils/TableGen/X86RecognizableInstr.h

[Jakob Stoklund Olesen]

On Oct 15, 2011, at 8:51 PM, Craig Topper wrote:

> Author: ctopper
> Date: Sat Oct 15 22:51:13 2011
> New Revision: 142105
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142105&view=rev
> Log:
> Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=142105&r1=142104&r2=142105&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Oct 15 22:51:13 2011
> @@ -1408,21 +1408,33 @@
> multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
>                    RegisterClass RC, X86MemOperand x86memop> {
>   def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
> -             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>;
> +             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, T8, VEX_4V;
>   def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
> -             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>;
> +             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, T8, VEX_4V;
> }

Note that TableGen infers the MCID::UnmodeledSideEffects flag on instructions without patterns.

You probably don't want that here since it disables a number of optimizations.

Use "let neverHasSideEffects = 1 in …" to disable the inference.

/jakob