[llvm-commits] [llvm] r142111 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

[Cameron Zwarich]

Author: zwarich
Date: Sun Oct 16 01:38:10 2011
New Revision: 142111

URL: http://llvm.org/viewvc/llvm-project?rev=142111&view=rev
Log:
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
These missing flags show up as errors when running -verify-coalescing on
test-suite.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142111&r1=142110&r2=142111&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sun Oct 16 01:38:10 2011
@@ -1321,6 +1321,8 @@
                IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
 
 // Indexed stores
+
+let mayStore = 1, neverHasSideEffects = 1 in {
 def t2STR_PRE  : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
                             (ins rGPR:$Rt, t2addrmode_imm8:$addr),
                             AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
@@ -1397,7 +1399,7 @@
       [(set GPRnopc:$Rn_wb,
             (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
 }
-
+} // mayStore = 1, neverHasSideEffects = 1
 
 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
 // only.