[llvm-commits] [llvm] r140974 - in /llvm/trunk: lib/Target/X86/X86InstrArithmetic.td lib/Target/X86/X86InstrInfo.td test/MC/Disassembler/X86/intel-syntax.txt test/MC/Disassembler/X86/simple-tests.txt test/MC/Disassembler/X86/x86-32.txt
Craig Topper
craig.topper at gmail.com
Sun Oct 2 14:08:14 PDT 2011
Author: ctopper
Date: Sun Oct 2 16:08:12 2011
New Revision: 140974
URL: http://llvm.org/viewvc/llvm-project?rev=140974&view=rev
Log:
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt
llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=140974&r1=140973&r2=140974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Sun Oct 2 16:08:12 2011
@@ -866,11 +866,10 @@
// BinOpAI - Instructions like "add %eax, %eax, imm".
class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- Register areg>
+ Register areg, string operands>
: ITy<opcode, RawFrm, typeinfo,
(outs), (ins typeinfo.ImmOperand:$src),
- mnemonic, !strconcat("{$src, %", areg.AsmName, "|%",
- areg.AsmName, ", $src}"), []> {
+ mnemonic, operands, []> {
let ImmT = typeinfo.ImmEncoding;
let Uses = [areg];
let Defs = [areg];
@@ -935,10 +934,14 @@
def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
- def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
- def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
- def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
- def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
+ def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
+ "{$src, %al|AL, $src}">;
+ def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
+ "{$src, %ax|AX, $src}">;
+ def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
+ "{$src, %eax|EAX, $src}">;
+ def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
+ "{$src, %rax|RAX, $src}">;
}
}
@@ -1002,10 +1005,14 @@
def #NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
def #NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
- def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
- def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
- def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
- def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
+ def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
+ "{$src, %al|AL, $src}">;
+ def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
+ "{$src, %ax|AX, $src}">;
+ def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
+ "{$src, %eax|EAX, $src}">;
+ def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
+ "{$src, %rax|RAX, $src}">;
}
}
@@ -1065,10 +1072,14 @@
def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
- def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
- def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
- def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
- def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
+ def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
+ "{$src, %al|AL, $src}">;
+ def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
+ "{$src, %ax|AX, $src}">;
+ def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
+ "{$src, %eax|EAX, $src}">;
+ def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
+ "{$src, %rax|RAX, $src}">;
}
}
@@ -1126,9 +1137,13 @@
def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
- def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL>;
- def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX>;
- def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX>;
- def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX>;
+ def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
+ "{$src, %al|AL, $src}">;
+ def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
+ "{$src, %ax|AX, $src}">;
+ def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
+ "{$src, %eax|EAX, $src}">;
+ def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
+ "{$src, %rax|RAX, $src}">;
}
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=140974&r1=140973&r2=140974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Oct 2 16:08:12 2011
@@ -877,22 +877,22 @@
/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
/// 32-bit offset from the PC. These are only valid in x86-32 mode.
def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
- "mov{b}\t{$src, %al|%al, $src}", []>,
+ "mov{b}\t{$src, %al|AL, $src}", []>,
Requires<[In32BitMode]>;
def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
- "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
+ "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
Requires<[In32BitMode]>;
def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
- "mov{l}\t{$src, %eax|%eax, $src}", []>,
+ "mov{l}\t{$src, %eax|EAX, $src}", []>,
Requires<[In32BitMode]>;
def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
- "mov{b}\t{%al, $dst|$dst, %al}", []>,
+ "mov{b}\t{%al, $dst|$dst, AL}", []>,
Requires<[In32BitMode]>;
def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
- "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
+ "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
Requires<[In32BitMode]>;
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
- "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
+ "mov{l}\t{%eax, $dst|$dst, EAX}", []>,
Requires<[In32BitMode]>;
// FIXME: These definitions are utterly broken
@@ -901,13 +901,13 @@
// in question.
/*
def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
- "mov{q}\t{$src, %rax|%rax, $src}", []>;
+ "mov{q}\t{$src, %rax|RAX, $src}", []>;
def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
- "mov{q}\t{$src, %rax|%rax, $src}", []>;
+ "mov{q}\t{$src, %rax|RAX, $src}", []>;
def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
- "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
+ "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
- "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
+ "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
*/
@@ -1153,11 +1153,11 @@
}
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
- "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
- "xchg{l}\t{$src, %eax|%eax, $src}", []>;
+ "xchg{l}\t{$src, %eax|EAX, $src}", []>;
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
- "xchg{q}\t{$src, %rax|%rax, $src}", []>;
+ "xchg{q}\t{$src, %rax|RAX, $src}", []>;
Modified: llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt?rev=140974&r1=140973&r2=140974&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/intel-syntax.txt Sun Oct 2 16:08:12 2011
@@ -20,3 +20,60 @@
# CHECK: in AL, DX
0xec
+
+# CHECK: nop
+0x90
+
+# CHECK: xchg EAX, R8D
+0x41 0x90
+
+# CHECK: xchg RAX, R8
+0x49 0x90
+
+# CHECK: add AL, 0
+0x04 0x00
+
+# CHECK: add AX, 0
+0x66 0x05 0x00 0x00
+
+# CHECK: add EAX, 0
+0x05 0x00 0x00 0x00 0x00
+
+# CHECK: add RAX, 0
+0x48 0x05 0x00 0x00 0x00 0x00
+
+# CHECK: adc AL, 0
+0x14 0x00
+
+# CHECK: adc AX, 0
+0x66 0x15 0x00 0x00
+
+# CHECK: adc EAX, 0
+0x15 0x00 0x00 0x00 0x00
+
+# CHECK: adc RAX, 0
+0x48 0x15 0x00 0x00 0x00 0x00
+
+# CHECK: cmp AL, 0
+0x3c 0x00
+
+# CHECK: cmp AX, 0
+0x66 0x3d 0x00 0x00
+
+# CHECK: cmp EAX, 0
+0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: cmp RAX, 0
+0x48 0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: test AL, 0
+0xa8 0x00
+
+# CHECK: test AX, 0
+0x66 0xa9 0x00 0x00
+
+# CHECK: test EAX, 0
+0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: test RAX, 0
+0x48 0xa9 0x00 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=140974&r1=140973&r2=140974&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Oct 2 16:08:12 2011
@@ -309,5 +309,59 @@
# CHECK: invvpid (%rax), %rax
0x66 0x0f 0x38 0x81 0x00
+# CHECK: nop
+0x90
+
# CHECK: xchgl %r8d, %eax
0x41 0x90
+
+# CHECK: xchgq %r8, %rax
+0x49 0x90
+
+# CHECK: addb $0, %al
+0x04 0x00
+
+# CHECK: addw $0, %ax
+0x66 0x05 0x00 0x00
+
+# CHECK: addl $0, %eax
+0x05 0x00 0x00 0x00 0x00
+
+# CHECK: addq $0, %rax
+0x48 0x05 0x00 0x00 0x00 0x00
+
+# CHECK: adcb $0, %al
+0x14 0x00
+
+# CHECK: adcw $0, %ax
+0x66 0x15 0x00 0x00
+
+# CHECK: adcl $0, %eax
+0x15 0x00 0x00 0x00 0x00
+
+# CHECK: adcq $0, %rax
+0x48 0x15 0x00 0x00 0x00 0x00
+
+# CHECK: cmpb $0, %al
+0x3c 0x00
+
+# CHECK: cmpw $0, %ax
+0x66 0x3d 0x00 0x00
+
+# CHECK: cmpl $0, %eax
+0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: cmpq $0, %rax
+0x48 0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: testb $0, %al
+0xa8 0x00
+
+# CHECK: testw $0, %ax
+0x66 0xa9 0x00 0x00
+
+# CHECK: testl $0, %eax
+0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: testq $0, %rax
+0x48 0xa9 0x00 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=140974&r1=140973&r2=140974&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Sun Oct 2 16:08:12 2011
@@ -327,3 +327,60 @@
# CHECK: invvpid (%eax), %eax
0x66 0x0f 0x38 0x81 0x00
+
+# CHECK: nop
+0x90
+
+# CHECK: addb $0, %al
+0x04 0x00
+
+# CHECK: addw $0, %ax
+0x66 0x05 0x00 0x00
+
+# CHECK: addl $0, %eax
+0x05 0x00 0x00 0x00 0x00
+
+# CHECK: adcb $0, %al
+0x14 0x00
+
+# CHECK: adcw $0, %ax
+0x66 0x15 0x00 0x00
+
+# CHECK: adcl $0, %eax
+0x15 0x00 0x00 0x00 0x00
+
+# CHECK: cmpb $0, %al
+0x3c 0x00
+
+# CHECK: cmpw $0, %ax
+0x66 0x3d 0x00 0x00
+
+# CHECK: cmpl $0, %eax
+0x3d 0x00 0x00 0x00 0x00
+
+# CHECK: testb $0, %al
+0xa8 0x00
+
+# CHECK: testw $0, %ax
+0x66 0xa9 0x00 0x00
+
+# CHECK: testl $0, %eax
+0xa9 0x00 0x00 0x00 0x00
+
+# CHECK: movb 0, %al
+0xa0 0x00 0x00 0x00 0x00
+
+# CHECK: movw 0, %ax
+0x66 0xa1 0x00 0x00 0x00 0x00
+
+# CHECK: movl 0, %eax
+0xa1 0x00 0x00 0x00 0x00
+
+# CHECK: movb %al, 0
+0xa2 0x00 0x00 0x00 0x00
+
+# CHECK: movw %ax, 0
+0x66 0xa3 0x00 0x00 0x00 0x00
+
+# CHECK: movl %eax, 0
+0xa3 0x00 0x00 0x00 0x00
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