[llvm-commits] [llvm] r140349 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/select.ll

[Dan Gohman]

Author: djg
Date: Thu Sep 22 18:01:29 2011
New Revision: 140349

URL: http://llvm.org/viewvc/llvm-project?rev=140349&view=rev
Log:
Fix SimplifySelectCC to add newly created nodes to the DAGCombiner
worklist, as it may be possible to perform further optimization on them.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/ARM/select.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=140349&r1=140348&r2=140349&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Sep 22 18:01:29 2011
@@ -7500,10 +7500,13 @@
         SDValue Cond = DAG.getSetCC(DL,
                                     TLI.getSetCCResultType(N0.getValueType()),
                                     N0, N1, CC);
+        AddToWorkList(Cond.getNode());
         SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
                                         Cond, One, Zero);
+        AddToWorkList(CstOffset.getNode());
         CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
                             CstOffset);
+        AddToWorkList(CPIdx.getNode());
         return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
                            MachinePointerInfo::getConstantPool(), false,
                            false, Alignment);

Modified: llvm/trunk/test/CodeGen/ARM/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=140349&r1=140348&r2=140349&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select.ll Thu Sep 22 18:01:29 2011
@@ -76,12 +76,12 @@
 ; block generated, odds are good that we have close to the ideal code for this:
 ;
 ; CHECK-NEON:      _f8:
-; CHECK-NEON:      movw   [[REGISTER_1:r[0-9]+]], #1123
-; CHECK-NEON-NEXT: movs   [[REGISTER_2:r[0-9]+]], #0
-; CHECK-NEON-NEXT: cmp    r0, [[REGISTER_1]]
-; CHECK-NEON-NEXT: it     eq
-; CHECK-NEON-NEXT: moveq  [[REGISTER_2]], #4
-; CHECK-NEON-NEXT: adr    [[REGISTER_3:r[0-9]+]], LCPI
+; CHECK-NEON:      adr     r2, LCPI7_0
+; CHECK-NEON-NEXT: movw    r3, #1123
+; CHECK-NEON-NEXT: adds    r1, r2, #4
+; CHECK-NEON-NEXT: cmp     r0, r3
+; CHECK-NEON-NEXT: it      ne
+; CHECK-NEON-NEXT: movne   r1, r2
 ; CHECK-NEON-NEXT: ldr
 ; CHECK-NEON:      bx