[llvm-commits] [AVX] Add EXTRACT_SUBVECTOR to DAGCombine

[Rotem, Nadav]

Zvi's patch implements this optimization for subvectors. In some cases the new type-legalizer generates unneeded element inserts/extracts. The patch below implements the discussed optimization for vector elements. I plan to include it as part of the vector-select work. 


--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp	(revision 128837)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp	(working copy)
@@ -6507,7 +6508,20 @@
   // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
   // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
   SDValue EltNo = N->getOperand(1);
+  
+  // Extract (Insert (Elem, C), C) -> Elem
+  if (isa<ConstantSDNode>(EltNo) && InVec.getOpcode() == ISD::INSERT_VECTOR_ELT
+    && InVec.getOperand(2) == EltNo) {      
+      return InVec.getOperand(1);
+  }
 
+  // Extract (Insert (Elem, C), K) and (C!=K)-> Extract (Elem, K)
+  if (isa<ConstantSDNode>(EltNo) && InVec.getOpcode() == ISD::INSERT_VECTOR_ELT
+    && isa<ConstantSDNode>(InVec.getOperand(2)) && InVec.getOperand(2) != EltNo) {
+      return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
+        N->getValueType(0), InVec.getOperand(0), N->getOperand(1));
+  }
+



-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Rackover, Zvi
Sent: Tuesday, September 20, 2011 09:43
To: Bruno Cardoso Lopes
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [AVX] Add EXTRACT_SUBVECTOR to DAGCombine

Bruno, thanks for reviewing and investing effort in this.
The undef is only a special case of what this patch addresses.

Take for example one of the tests in the patch:
define <8 x i32> @test(<8 x i32> %v1, <8 x i32> %v2) {
  %1 = add <8 x i32> %v1, %v2
  %2 = add <8 x i32> %1, %v1
  ret <8 x i32> %2
}

Running on TOT gives:
   vextractf128    $1, %ymm1, %xmm3
   vextractf128    $1, %ymm0, %xmm2
   vpaddd  %xmm3, %xmm2, %xmm3
   vpaddd  %xmm1, %xmm0, %xmm1
   vinsertf128     $1, %xmm3, %ymm1, %ymm3  <--------
   vextractf128    $1, %ymm3, %xmm1               <---------
   vpaddd  %xmm2, %xmm1, %xmm1
   vpaddd  %xmm0, %xmm3, %xmm0
   vinsertf128     $1, %xmm1, %ymm0, %ymm0

Running with the patch applied gives:
   vextractf128    $1, %ymm1, %xmm3
   vextractf128    $1, %ymm0, %xmm2
   vpaddd  %xmm3, %xmm2, %xmm3
   vpaddd  %xmm2, %xmm3, %xmm2
   vpaddd  %xmm1, %xmm0, %xmm1
   vpaddd  %xmm0, %xmm1, %xmm0
   vinsertf128     $1, %xmm2, %ymm0, %ymm0

We can optimize away redundant insert_subvector/extract_subvector pairs by applying the following transforms:
EXTRACT_SV( INSERT_SV( V1, V2, I ), I)         ----> V2
EXTRACT_SV( INSERT_SV( V1, V2, I1 ), I2)     ----> EXTRACT_SV( V1, I2 )

I thought it would be right to make this optimization target-interdependent, but if it should be X86-specific, where should it be located?

Thanks, Zvi

-----Original Message-----
From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] 
Sent: Tuesday, September 20, 2011 02:41
To: Rackover, Zvi
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [AVX] Add EXTRACT_SUBVECTOR to DAGCombine

Hi Zvi,

On Mon, Sep 19, 2011 at 11:31 AM, Rackover, Zvi <zvi.rackover at intel.com> wrote:
> Hi Bruno and other codegen people,
>
>
>
> Please review the attached patch and commit if acceptable.
>
> I categorized this patch as AVX, since I am not aware of other cases in X86
> where it shows any benefit.

You should be looking in INSERT_SUBVECTOR instead of extract, because
is the undef
being inserted in the upper part that you want to catch. I provided
another fix for this in r140097

Thanks

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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