[llvm-commits] [llvm] r139994 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

[Nadav Rotem]

Author: nadav
Date: Sun Sep 18 05:29:29 2011
New Revision: 139994

URL: http://llvm.org/viewvc/llvm-project?rev=139994&view=rev
Log:
white space cleanups

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=139994&r1=139993&r2=139994&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Sun Sep 18 05:29:29 2011
@@ -61,8 +61,8 @@
   // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
   // SINT_TO_FLOAT and SHR on vectors isn't legal.
   SDValue ExpandUINT_TO_FLOAT(SDValue Op);
-  // Implement vselect in terms of XOR, AND,OR when blend is not supported
-  //  by the target.
+  // Implement vselect in terms of XOR, AND, OR when blend is not supported
+  // by the target.
   SDValue ExpandVSELECT(SDValue Op);
   SDValue ExpandFNEG(SDValue Op);
   // Implements vector promotion; this is essentially just bitcasting the
@@ -277,9 +277,8 @@
   // AND,OR,XOR, we will have to scalarize the op.
   if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
       !TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
-      !TLI.isOperationLegalOrCustom(ISD::OR, VT)) {
-    return DAG.UnrollVectorOp(Op.getNode());
-  }
+      !TLI.isOperationLegalOrCustom(ISD::OR, VT))
+        return DAG.UnrollVectorOp(Op.getNode());
 
   assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
   // Bitcast the operands to be the same type as the mask.