[llvm-commits] [llvm] r139739 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/basic-thumb2-instructions.s
Jim Grosbach
grosbach at apple.com
Wed Sep 14 14:24:41 PDT 2011
Author: grosbach
Date: Wed Sep 14 16:24:41 2011
New Revision: 139739
URL: http://llvm.org/viewvc/llvm-project?rev=139739&view=rev
Log:
Thumb2 assembly parsing and encoding for MVN.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139739&r1=139738&r2=139739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep 14 16:24:41 2011
@@ -458,47 +458,6 @@
}
-/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
-/// unary operation that produces a value. These are predicable and can be
-/// changed to modify CPSR.
-multiclass T2I_un_irs<bits<4> opcod, string opc,
- InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
- PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
- // shifted imm
- def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
- opc, "\t$Rd, $imm",
- [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
- let isAsCheapAsAMove = Cheap;
- let isReMaterializable = ReMat;
- let Inst{31-27} = 0b11110;
- let Inst{25} = 0;
- let Inst{24-21} = opcod;
- let Inst{19-16} = 0b1111; // Rn
- let Inst{15} = 0;
- }
- // register
- def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
- opc, ".w\t$Rd, $Rm",
- [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
- let Inst{31-27} = 0b11101;
- let Inst{26-25} = 0b01;
- let Inst{24-21} = opcod;
- let Inst{19-16} = 0b1111; // Rn
- let Inst{14-12} = 0b000; // imm3
- let Inst{7-6} = 0b00; // imm2
- let Inst{5-4} = 0b00; // type
- }
- // shifted register
- def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
- opc, ".w\t$Rd, $ShiftedRm",
- [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
- let Inst{31-27} = 0b11101;
- let Inst{26-25} = 0b01;
- let Inst{24-21} = opcod;
- let Inst{19-16} = 0b1111; // Rn
- }
-}
-
/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
/// binary operation that produces a value. These are predicable and can be
/// changed to modify CPSR.
@@ -2247,13 +2206,53 @@
BinOpFrag<(or node:$LHS, (not node:$RHS))>,
"t2ORN", 0, "">;
+/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
+/// unary operation that produces a value. These are predicable and can be
+/// changed to modify CPSR.
+multiclass T2I_un_irs<bits<4> opcod, string opc,
+ InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
+ PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
+ // shifted imm
+ def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
+ opc, "\t$Rd, $imm",
+ [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
+ let isAsCheapAsAMove = Cheap;
+ let isReMaterializable = ReMat;
+ let Inst{31-27} = 0b11110;
+ let Inst{25} = 0;
+ let Inst{24-21} = opcod;
+ let Inst{19-16} = 0b1111; // Rn
+ let Inst{15} = 0;
+ }
+ // register
+ def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
+ opc, ".w\t$Rd, $Rm",
+ [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
+ let Inst{31-27} = 0b11101;
+ let Inst{26-25} = 0b01;
+ let Inst{24-21} = opcod;
+ let Inst{19-16} = 0b1111; // Rn
+ let Inst{14-12} = 0b000; // imm3
+ let Inst{7-6} = 0b00; // imm2
+ let Inst{5-4} = 0b00; // type
+ }
+ // shifted register
+ def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
+ opc, ".w\t$Rd, $ShiftedRm",
+ [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
+ let Inst{31-27} = 0b11101;
+ let Inst{26-25} = 0b01;
+ let Inst{24-21} = opcod;
+ let Inst{19-16} = 0b1111; // Rn
+ }
+}
+
// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
let AddedComplexity = 1 in
defm t2MVN : T2I_un_irs <0b0011, "mvn",
IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
UnOpFrag<(not node:$Src)>, 1, 1>;
-
let AddedComplexity = 1 in
def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
(t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
@@ -3820,3 +3819,9 @@
(t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
def : t2InstAlias<"ldrsh${p} $Rt, $addr",
(t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
+
+// Alias for MVN without the ".w" optional width specifier.
+def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
+ (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
+ (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139739&r1=139738&r2=139739&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Sep 14 16:24:41 2011
@@ -1123,6 +1123,51 @@
@ CHECK: it eq @ encoding: [0x08,0xbf]
@ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3]
+
+ at ------------------------------------------------------------------------------
+@ MVN(immediate)
+ at ------------------------------------------------------------------------------
+ mvns r8, #21
+ mvn r0, #0x3fc0000
+ mvns r0, #0x3fc0000
+ itte eq
+ mvnseq r1, #12
+ mvneq r1, #12
+ mvnne r1, #12
+
+@ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08]
+@ CHECK: mvn r0, #66846720 @ encoding: [0x6f,0xf0,0x7f,0x70]
+@ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70]
+@ CHECK: itte eq @ encoding: [0x06,0xbf]
+@ CHECK: mvnseq r1, #12 @ encoding: [0x7f,0xf0,0x0c,0x01]
+@ CHECK: mvneq r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01]
+@ CHECK: mvnne r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01]
+
+
+ at ------------------------------------------------------------------------------
+@ MVN(register)
+ at ------------------------------------------------------------------------------
+ mvn r2, r3
+ mvns r2, r3
+ mvn r5, r6, lsl #19
+ mvn r5, r6, lsr #9
+ mvn r5, r6, asr #4
+ mvn r5, r6, ror #6
+ mvn r5, r6, rrx
+ it eq
+ mvneq r2, r3
+
+@ CHECK: mvn.w r2, r3 @ encoding: [0x6f,0xea,0x03,0x02]
+@ CHECK: mvns r2, r3 @ encoding: [0xda,0x43]
+@ CHECK: mvn.w r5, r6, lsl #19 @ encoding: [0x6f,0xea,0xc6,0x45]
+@ CHECK: mvn.w r5, r6, lsr #9 @ encoding: [0x6f,0xea,0x56,0x25]
+@ CHECK: mvn.w r5, r6, asr #4 @ encoding: [0x6f,0xea,0x26,0x15]
+@ CHECK: mvn.w r5, r6, ror #6 @ encoding: [0x6f,0xea,0xb6,0x15]
+@ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05]
+@ CHECK: it eq @ encoding: [0x08,0xbf]
+@ CHECK: mvneq r2, r3 @ encoding: [0xda,0x43]
+
+
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@ IT
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