[llvm-commits] [llvm] r139630 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td
Nadav Rotem
nadav.rotem at intel.com
Tue Sep 13 12:56:38 PDT 2011
Author: nadav
Date: Tue Sep 13 14:56:38 2011
New Revision: 139630
URL: http://llvm.org/viewvc/llvm-project?rev=139630&view=rev
Log:
swap vselect operand order - pr10907
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139630&r1=139629&r2=139630&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Sep 13 14:56:38 2011
@@ -5958,31 +5958,31 @@
let Predicates = [HasAVX] in {
def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
(v16i8 VR128:$src2))),
- (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+ (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
(v4i32 VR128:$src2))),
- (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+ (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
(v4f32 VR128:$src2))),
- (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+ (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
(v2i64 VR128:$src2))),
- (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+ (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
(v2f64 VR128:$src2))),
- (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+ (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
(v8i32 VR256:$src2))),
- (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+ (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
(v8f32 VR256:$src2))),
- (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+ (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
(v4i64 VR256:$src2))),
- (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+ (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
(v4f64 VR256:$src2))),
- (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+ (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
}
/// SS41I_ternary_int - SSE 4.1 ternary operator
@@ -6012,19 +6012,19 @@
let Predicates = [HasSSE41] in {
def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
(v16i8 VR128:$src2))),
- (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
+ (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
(v4i32 VR128:$src2))),
- (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+ (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
(v4f32 VR128:$src2))),
- (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+ (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
(v2i64 VR128:$src2))),
- (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+ (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
(v2f64 VR128:$src2))),
- (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+ (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
}
let Predicates = [HasAVX] in
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