[llvm-commits] [llvm] r139606 - in /llvm/trunk: lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-thumb2-instructions.s

Owen Anderson resistor at mac.com
Tue Sep 13 10:34:32 PDT 2011


Author: resistor
Date: Tue Sep 13 12:34:32 2011
New Revision: 139606

URL: http://llvm.org/viewvc/llvm-project?rev=139606&view=rev
Log:
Fix encoding of Thumb2 shifted register operands with RRX shifts.

Modified:
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=139606&r1=139605&r2=139606&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Sep 13 12:34:32 2011
@@ -1277,6 +1277,7 @@
   case ARM_AM::lsl: SBits = 0x0; break;
   case ARM_AM::lsr: SBits = 0x2; break;
   case ARM_AM::asr: SBits = 0x4; break;
+  case ARM_AM::rrx: // FALLTHROUGH
   case ARM_AM::ror: SBits = 0x6; break;
   }
 

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139606&r1=139605&r2=139606&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Tue Sep 13 12:34:32 2011
@@ -1029,3 +1029,11 @@
 @ CHECK: nopne                          @ encoding: [0x00,0xbf]
 @ CHECK: subne	r5, r6, r7              @ encoding: [0xf5,0x1b]
 @ CHECK: addeq	r1, r2, #4              @ encoding: [0x11,0x1d]
+
+ at ------------------------------------------------------------------------------
+@ SUB (register)
+ at ------------------------------------------------------------------------------
+        sub.w r5, r2, r12, rrx
+
+@ CHECK: sub.w r5, r2, r12, rrx        @ encoding: [0xa2,0xeb,0x3c,0x05]
+





More information about the llvm-commits mailing list