[llvm-commits] [llvm] r139491 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td

[Nadav Rotem]

Author: nadav
Date: Mon Sep 12 03:41:50 2011
New Revision: 139491

URL: http://llvm.org/viewvc/llvm-project?rev=139491&view=rev
Log:
Format patterns, remove unused X86blend patterns

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139491&r1=139490&r2=139491&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Sep 12 03:41:50 2011
@@ -58,9 +58,6 @@
 def X86psignd  : SDNode<"X86ISD::PSIGND",
                  SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
                                       SDTCisSameAs<0,2>]>>;
-def X86blendv : SDNode<"X86ISD::BLENDV",
-                 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
-                                      SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
 def X86pextrw  : SDNode<"X86ISD::PEXTRW",

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139491&r1=139490&r2=139491&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Sep 12 03:41:50 2011
@@ -5930,27 +5930,34 @@
                                          memopv32i8, int_x86_avx_blendv_ps_256>;
 
 let Predicates = [HasAVX] in {
-def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
- VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 
 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
- (v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+                  (v16i8 VR128:$src2))),
+    (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
- (v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+                  (v4i32 VR128:$src2))),
+    (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
- (v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+                  (v4f32 VR128:$src2))),
+    (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
- (v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+                  (v2i64 VR128:$src2))),
+    (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
- (v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
+                  (v2f64 VR128:$src2))),
+    (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
- (v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+                  (v8i32 VR256:$src2))),
+    (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
- (v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+                  (v8f32 VR256:$src2))),
+    (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
- (v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+                  (v4i64 VR256:$src2))),
+    (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
- (v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
+                  (v4f64 VR256:$src2))),
+    (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
 
 }
 
@@ -5979,19 +5986,22 @@
 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
 
 let Predicates = [HasSSE41] in {
-def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
- VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
 
-  def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
- (v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
- (v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
- (v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
- (v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
-  def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
- (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
+                  (v16i8 VR128:$src2))),
+    (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
+def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
+                  (v4i32 VR128:$src2))),
+    (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
+                  (v4f32 VR128:$src2))),
+    (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
+                  (v2i64 VR128:$src2))),
+    (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
+def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
+                  (v2f64 VR128:$src2))),
+    (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
 }
 
 let Predicates = [HasAVX] in