[llvm-commits] [llvm] r139285 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/Generic/promote-integers.ll
Duncan Sands
baldrick at free.fr
Thu Sep 8 11:17:54 PDT 2011
Now I come to think about it, is there any need to custom lower: since vselect
maps directly onto processor instructions, can't it be done entirely using
tablegen patterns? That said, I have no idea how tablegen works, so feel free
to ignore me if this makes no sense :)
Ciao, Duncan.
On 08/09/11 18:49, Bruno Cardoso Lopes wrote:
> Cool!
>
> On Thu, Sep 8, 2011 at 1:11 AM, Nadav Rotem<nadav.rotem at intel.com> wrote:
>> Author: nadav
>> Date: Thu Sep 8 03:11:19 2011
>> New Revision: 139285
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=139285&view=rev
>> Log:
>> Add X86-SSE4 codegen support for vector-select.
>>
>>
>> Modified:
>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> llvm/trunk/lib/Target/X86/X86ISelLowering.h
>> llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
>> llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> llvm/trunk/test/CodeGen/Generic/promote-integers.ll
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 8 03:11:19 2011
>> @@ -917,6 +917,13 @@
>> setOperationAction(ISD::SHL, MVT::v4i32, Custom);
>> setOperationAction(ISD::SHL, MVT::v16i8, Custom);
>>
>> + setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
>> + setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
>> + setOperationAction(ISD::VSELECT, MVT::v16i8, Custom);
>> + setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
>> + setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
>> + setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
>> +
>> // i8 and i16 vectors are custom , because the source register and source
>> // source memory operand types are not the same width. f32 vectors are
>> // custom since the immediate controlling the insert encodes additional
>> @@ -8684,6 +8691,32 @@
>> return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
>> }
>>
>> +SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG&DAG) const {
>> + SDValue Cond = Op.getOperand(0);
>> + SDValue Op1 = Op.getOperand(1);
>> + SDValue Op2 = Op.getOperand(2);
>> + DebugLoc DL = Op.getDebugLoc();
>> +
>> + SDValue Ops[] = {Cond, Op1, Op2};
>> +
>> + assert(Op1.getValueType().isVector()&& "Op1 must be a vector");
>> + assert(Op2.getValueType().isVector()&& "Op2 must be a vector");
>> + assert(Cond.getValueType().isVector()&& "Cond must be a vector");
>> + assert(Op1.getValueType() == Op2.getValueType()&& "Type mismatch");
>> +
>> + switch (Op1.getValueType().getSimpleVT().SimpleTy) {
>> + default: break;
>> + case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> + case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> + case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> + case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> + case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
>> + }
>
> This also breaks 80-columns restriction
>
>> + return SDValue();
>> +}
>> +
>> +
>> // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
>> // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
>> // from the AND / OR.
>> @@ -10350,6 +10383,7 @@
>> case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
>> case ISD::SETCC: return LowerSETCC(Op, DAG);
>> case ISD::SELECT: return LowerSELECT(Op, DAG);
>> + case ISD::VSELECT: return LowerVSELECT(Op, DAG);
>> case ISD::BRCOND: return LowerBRCOND(Op, DAG);
>> case ISD::JumpTable: return LowerJumpTable(Op, DAG);
>> case ISD::VASTART: return LowerVASTART(Op, DAG);
>>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Sep 8 03:11:19 2011
>> @@ -175,8 +175,10 @@
>> /// PSIGNB/W/D - Copy integer sign.
>> PSIGNB, PSIGNW, PSIGND,
>>
>> - /// PBLENDVB - Variable blend
>> + /// BLENDVXX family of opcodes
>> PBLENDVB,
>> + BLENDVPD,
>> + BLENDVPS,
>>
>> /// FMAX, FMIN - Floating point max and min.
>> ///
>> @@ -809,6 +811,7 @@
>> SDValue LowerSETCC(SDValue Op, SelectionDAG&DAG) const;
>> SDValue LowerVSETCC(SDValue Op, SelectionDAG&DAG) const;
>> SDValue LowerSELECT(SDValue Op, SelectionDAG&DAG) const;
>> + SDValue LowerVSELECT(SDValue Op, SelectionDAG&DAG) const;
>> SDValue LowerBRCOND(SDValue Op, SelectionDAG&DAG) const;
>> SDValue LowerMEMSET(SDValue Op, SelectionDAG&DAG) const;
>> SDValue LowerJumpTable(SDValue Op, SelectionDAG&DAG) const;
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Sep 8 03:11:19 2011
>> @@ -58,9 +58,15 @@
>> def X86psignd : SDNode<"X86ISD::PSIGND",
>> SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
>> SDTCisSameAs<0,2>]>>;
>> -def X86pblendv : SDNode<"X86ISD::PBLENDVB",
>> +def X86pblendvb : SDNode<"X86ISD::PBLENDVB",
>> SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
>> SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
>> +def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
>> + SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
>> + SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
>> +def X86blendvps : SDNode<"X86ISD::BLENDVPS",
>> + SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
>> + SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
>> def X86pextrb : SDNode<"X86ISD::PEXTRB",
>> SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
>> def X86pextrw : SDNode<"X86ISD::PEXTRW",
>>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
>> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep 8 03:11:19 2011
>> @@ -5843,7 +5843,7 @@
>> defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
>> memopv32i8, int_x86_avx_blendv_ps_256>;
>>
>> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, VR128:$src3),
>> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3),
>> (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>,
>> Requires<[HasAVX]>;
>>
>> @@ -5871,8 +5871,12 @@
>> defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
>> defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
>>
>> -def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
>> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
>> (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>> +def : Pat<(X86blendvpd XMM0, VR128:$src1, VR128:$src2),
>> + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>> +def : Pat<(X86blendvps XMM0, VR128:$src1, VR128:$src2),
>> + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
>
> I will do it this time, but next time can you add the AVX versions
> when adding SSE ones? Usually all you need are the same patterns but
> with a different predicate!
>
>> let Predicates = [HasAVX] in
>> def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
>>
>> Modified: llvm/trunk/test/CodeGen/Generic/promote-integers.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=139285&r1=139284&r2=139285&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (original)
>> +++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll Thu Sep 8 03:11:19 2011
>> @@ -3,8 +3,8 @@
>>
>> ; This test is the poster-child for integer-element-promotion.
>> ; Until this feature is complete, we mark this test as expected to fail.
>> -; XFAIL: *
>> ; CHECK: vector_code
>> +; CHECK: blend
>> ; CHECK: ret
>> define<4 x float> @vector_code(<4 x i64> %A,<4 x i64> %B,<4 x float> %R0,<4 x float> %R1 ) {
>> %C = icmp eq<4 x i64> %A, %B
>>
>>
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>
>
>
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