[llvm-commits] [llvm] r139256 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb-tests.txt
Owen Anderson
resistor at mac.com
Wed Sep 7 14:10:42 PDT 2011
Author: resistor
Date: Wed Sep 7 16:10:42 2011
New Revision: 139256
URL: http://llvm.org/viewvc/llvm-project?rev=139256&view=rev
Log:
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=139256&r1=139255&r2=139256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep 7 16:10:42 2011
@@ -3294,6 +3294,110 @@
[(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
imm:$cp))]>,
Requires<[IsThumb2]>;
+//===----------------------------------------------------------------------===//
+// Coprocessor load/store -- for disassembly only
+//
+class T2CI<dag oops, dag iops, string opc, string asm>
+ : T2I<oops, iops, NoItinerary, opc, asm, []> {
+ let Inst{27-25} = 0b110;
+}
+
+multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
+ def _OFFSET : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+ opc, "\tp$cop, cr$CRd, $addr"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 1; // P = 1
+ let Inst{21} = 0; // W = 0
+ let Inst{22} = 0; // D = 0
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def _PRE : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+ opc, "\tp$cop, cr$CRd, $addr!"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 1; // P = 1
+ let Inst{21} = 1; // W = 1
+ let Inst{22} = 0; // D = 0
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def _POST : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+ opc, "\tp$cop, cr$CRd, $addr"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 0; // P = 0
+ let Inst{21} = 1; // W = 1
+ let Inst{22} = 0; // D = 0
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def _OPTION : T2CI<(outs),
+ (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
+ opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 0; // P = 0
+ let Inst{23} = 1; // U = 1
+ let Inst{21} = 0; // W = 0
+ let Inst{22} = 0; // D = 0
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def L_OFFSET : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+ !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 1; // P = 1
+ let Inst{21} = 0; // W = 0
+ let Inst{22} = 1; // D = 1
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def L_PRE : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
+ !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 1; // P = 1
+ let Inst{21} = 1; // W = 1
+ let Inst{22} = 1; // D = 1
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def L_POST : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
+ postidx_imm8s4:$offset),
+ !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 0; // P = 0
+ let Inst{21} = 1; // W = 1
+ let Inst{22} = 1; // D = 1
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+
+ def L_OPTION : T2CI<(outs),
+ (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
+ !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
+ let Inst{31-28} = op31_28;
+ let Inst{24} = 0; // P = 0
+ let Inst{23} = 1; // U = 1
+ let Inst{21} = 0; // W = 0
+ let Inst{22} = 1; // D = 1
+ let Inst{20} = load;
+ let DecoderMethod = "DecodeCopMemInstruction";
+ }
+}
+
+defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
+defm t2STC : T2LdStCop<0b1111, 0, "stc">;
+
//===----------------------------------------------------------------------===//
// Move between special register and ARM core register -- for disassembly only
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139256&r1=139255&r2=139256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Sep 7 16:10:42 2011
@@ -997,6 +997,22 @@
case ARM::STCL_PRE:
case ARM::STCL_POST:
case ARM::STCL_OPTION:
+ case ARM::t2LDC_OFFSET:
+ case ARM::t2LDC_PRE:
+ case ARM::t2LDC_POST:
+ case ARM::t2LDC_OPTION:
+ case ARM::t2LDCL_OFFSET:
+ case ARM::t2LDCL_PRE:
+ case ARM::t2LDCL_POST:
+ case ARM::t2LDCL_OPTION:
+ case ARM::t2STC_OFFSET:
+ case ARM::t2STC_PRE:
+ case ARM::t2STC_POST:
+ case ARM::t2STC_OPTION:
+ case ARM::t2STCL_OFFSET:
+ case ARM::t2STCL_PRE:
+ case ARM::t2STCL_POST:
+ case ARM::t2STCL_OPTION:
if (coproc == 0xA || coproc == 0xB)
return MCDisassembler::Fail;
break;
@@ -1021,6 +1037,12 @@
case ARM::STCL_POST:
case ARM::LDC2L_POST:
case ARM::STC2L_POST:
+ case ARM::t2LDC_OPTION:
+ case ARM::t2LDCL_OPTION:
+ case ARM::t2STC_OPTION:
+ case ARM::t2STCL_OPTION:
+ case ARM::t2LDCL_POST:
+ case ARM::t2STCL_POST:
break;
default:
Inst.addOperand(MCOperand::CreateReg(0));
@@ -1040,6 +1062,8 @@
switch (Inst.getOpcode()) {
case ARM::LDCL_POST:
case ARM::STCL_POST:
+ case ARM::t2LDCL_POST:
+ case ARM::t2STCL_POST:
case ARM::LDC2L_POST:
case ARM::STC2L_POST:
imm |= U << 8;
@@ -1051,6 +1075,10 @@
case ARM::STCL_OPTION:
case ARM::STC2_OPTION:
case ARM::STC2L_OPTION:
+ case ARM::t2LDC_OPTION:
+ case ARM::t2LDCL_OPTION:
+ case ARM::t2STC_OPTION:
+ case ARM::t2STCL_OPTION:
Inst.addOperand(MCOperand::CreateImm(imm));
break;
default:
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=139256&r1=139255&r2=139256&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Wed Sep 7 16:10:42 2011
@@ -218,11 +218,8 @@
# CHECK: pld [r5, #30]
0x95 0xf8 0x1e 0xf0
-# Test disabled as it was originally checking for
-# the ARM encoding of stc2, and thumb2 stc2 is
-# not implemented yet.
-# CHECK-: stc2 p12, cr15, [r9], {137}
-#0x89 0xfc 0x89 0xfc
+# CHECK: stc p12, cr15, [r9], {137}
+0x89 0xfc 0x89 0xfc
# CHECK: vmov r1, r0, d11
0x50 0xec 0x1b 0x1b
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