[llvm-commits] [llvm] r138980 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
James Molloy
james.molloy at arm.com
Fri Sep 2 00:11:37 PDT 2011
Hi Owen,
I like that change, but I was explicitly asked by Jim in his previous
post-commit review not to typedef away namespacing, which is why the
"MCDisassembler::" prefix ended up being added everywhere as part of my patch
fixup :(
It looks better to me, as long as it's OK with Jim?
James
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Owen Anderson
> Sent: 02 September 2011 00:24
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [llvm] r138980 -
> /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>
> Author: resistor
> Date: Thu Sep 1 18:23:50 2011
> New Revision: 138980
>
> URL: http://llvm.org/viewvc/llvm-project?rev=138980&view=rev
> Log:
> Fix 80 columns violations.
>
> Modified:
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=1389
> 80&r1=138979&r2=138980&view=diff
> ===========================================================================
> ===
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep 1
> 18:23:50 2011
> @@ -26,7 +26,9 @@
>
> using namespace llvm;
>
> -static bool Check(MCDisassembler::DecodeStatus &Out,
> MCDisassembler::DecodeStatus In) {
> +typedef MCDisassembler::DecodeStatus DecodeStatus;
> +
> +static bool Check(DecodeStatus &Out, DecodeStatus In) {
> switch (In) {
> case MCDisassembler::Success:
> // Out stays the same.
> @@ -43,198 +45,198 @@
>
> // Forward declare these because the autogenerated code will reference
> them.
> // Definitions are further down.
> -static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
> unsigned RegNo, uint64_t
> Address,
> const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
> unsigned RegNo,
> uint64_t Address,
> const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder);
>
> -static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
>
> -static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address,
> const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
>
> -static MCDisassembler::DecodeStatus
> DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &
> Inst,
> unsigned Insn,
> uint64_t Adddress,
> const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst
> &Inst,unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst
> &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst
> &Inst, uint16_t Val,
> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst
> &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst,
> uint16_t Insn,
> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst
> &Inst,unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus
> DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder);
> -static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned
> Val,
> +static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
>
> #include "ARMGenDisassemblerTables.inc"
> @@ -257,7 +259,7 @@
> return instInfoARM;
> }
>
> -MCDisassembler::DecodeStatus ARMDisassembler::getInstruction(MCInst &MI,
> uint64_t &Size,
> +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> const MemoryObject &Region,
> uint64_t Address,
> raw_ostream &os) const {
> @@ -276,7 +278,7 @@
> (bytes[0] << 0);
>
> // Calling the auto-generated decoder function.
> - MCDisassembler::DecodeStatus result = decodeARMInstruction32(MI, insn,
> Address, this);
> + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
> if (result != MCDisassembler::Fail) {
> Size = 4;
> return result;
> @@ -307,7 +309,8 @@
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return
> MCDisassembler::Fail;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this))
> + return MCDisassembler::Fail;
> return result;
> }
>
> @@ -317,7 +320,8 @@
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return
> MCDisassembler::Fail;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this))
> + return MCDisassembler::Fail;
> return result;
> }
>
> @@ -327,7 +331,8 @@
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return
> MCDisassembler::Fail;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this))
> + return MCDisassembler::Fail;
> return result;
> }
>
> @@ -440,7 +445,7 @@
> }
> }
>
> -MCDisassembler::DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI,
> uint64_t &Size,
> +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> const MemoryObject &Region,
> uint64_t Address,
> raw_ostream &os) const {
> @@ -453,7 +458,7 @@
> }
>
> uint16_t insn16 = (bytes[1] << 8) | bytes[0];
> - MCDisassembler::DecodeStatus result = decodeThumbInstruction16(MI,
> insn16, Address, this);
> + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address,
> this);
> if (result != MCDisassembler::Fail) {
> Size = 2;
> AddThumbPredicate(MI);
> @@ -598,7 +603,7 @@
> ARM::R12, ARM::SP, ARM::LR, ARM::PC
> };
>
> -static MCDisassembler::DecodeStatus DecodeGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo > 15)
> return MCDisassembler::Fail;
> @@ -608,21 +613,21 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo == 15) return MCDisassembler::Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static MCDisassembler::DecodeStatus DecodetGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo > 7)
> return MCDisassembler::Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static MCDisassembler::DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> unsigned Register = 0;
> switch (RegNo) {
> @@ -652,7 +657,7 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecoderGPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> @@ -669,7 +674,7 @@
> ARM::S28, ARM::S29, ARM::S30, ARM::S31
> };
>
> -static MCDisassembler::DecodeStatus DecodeSPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo > 31)
> return MCDisassembler::Fail;
> @@ -690,7 +695,7 @@
> ARM::D28, ARM::D29, ARM::D30, ARM::D31
> };
>
> -static MCDisassembler::DecodeStatus DecodeDPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo > 31)
> return MCDisassembler::Fail;
> @@ -700,14 +705,14 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo > 7)
> return MCDisassembler::Fail;
> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 15)
> @@ -723,7 +728,7 @@
> };
>
>
> -static MCDisassembler::DecodeStatus DecodeQPRRegisterClass(llvm::MCInst
> &Inst, unsigned RegNo,
> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned
> RegNo,
> uint64_t Address, const void *Decoder)
> {
> if (RegNo > 31)
> return MCDisassembler::Fail;
> @@ -734,7 +739,7 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodePredicateOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> if (Val == 0xF) return MCDisassembler::Fail;
> // AL predicate is not allowed on Thumb1 branches.
> @@ -748,7 +753,7 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val)
> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> @@ -757,7 +762,7 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> uint32_t imm = Val & 0xFF;
> uint32_t rot = (Val & 0xF00) >> 7;
> @@ -766,16 +771,17 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeSORegImmOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> unsigned imm = fieldFromInstruction32(Val, 7, 5);
>
> // Register-immediate
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> switch (type) {
> @@ -802,17 +808,19 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeSORegRegOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> unsigned Rs = fieldFromInstruction32(Val, 8, 4);
>
> // Register-register
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> switch (type) {
> @@ -835,52 +843,57 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> // Empty register lists are not allowed.
> if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
> for (unsigned i = 0; i < 16; ++i) {
> if (Val & (1 << i)) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeSPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> unsigned regs = Val & 0xFF;
>
> - if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
> + return MCDisassembler::Fail;
> for (unsigned i = 0; i < (regs - 1); ++i) {
> - if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeDPRRegListOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> unsigned regs = (Val & 0xFF) / 2;
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
> + return MCDisassembler::Fail;
> for (unsigned i = 0; i < (regs - 1); ++i) {
> - if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void
> *Decoder) {
> // This operand encodes a mask of contiguous zeros between a specified
> MSB
> // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
> @@ -895,9 +908,9 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeCopMemInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
> @@ -932,7 +945,8 @@
>
> Inst.addOperand(MCOperand::CreateImm(coproc));
> Inst.addOperand(MCOperand::CreateImm(CRd));
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> switch (Inst.getOpcode()) {
> case ARM::LDC_OPTION:
> case ARM::LDCL_OPTION:
> @@ -1005,7 +1019,8 @@
> case ARM::STCL_PRE:
> case ARM::STCL_POST:
> case ARM::STCL_OPTION:
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1014,10 +1029,10 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -1038,13 +1053,15 @@
> case ARM::STRT_POST_IMM:
> case ARM::STRBT_POST_REG:
> case ARM::STRBT_POST_IMM:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> // On loads, the writeback operand comes after Rt.
> switch (Inst.getOpcode()) {
> @@ -1056,13 +1073,15 @@
> case ARM::LDRBT_POST_IMM:
> case ARM::LDRT_POST_REG:
> case ARM::LDRT_POST_IMM:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> ARM_AM::AddrOpc Op = ARM_AM::add;
> if (!fieldFromInstruction32(Insn, 23, 1))
> @@ -1075,10 +1094,12 @@
> else if (!P && writeback)
> idx_mode = ARMII::IndexModePost;
>
> - if (writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler::SoftFail;
> // UNPREDICTABLE
> + if (writeback && (Rn == 15 || Rn == Rt))
> + S = MCDisassembler::SoftFail; // UNPREDICTABLE
>
> if (reg) {
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
> switch( fieldFromInstruction32(Insn, 5, 2)) {
> case 0:
> @@ -1106,14 +1127,15 @@
> Inst.addOperand(MCOperand::CreateImm(tmp));
> }
>
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeSORegMemOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> @@ -1137,8 +1159,10 @@
> break;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> unsigned shift;
> if (U)
> shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
> @@ -1149,10 +1173,10 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -1176,8 +1200,8 @@
> case ARM::LDRD_POST:
> if (Rt & 0x1) return MCDisassembler::Fail;
> break;
> - default:
> - break;
> + default:
> + break;
> }
>
> if (writeback) { // Writeback
> @@ -1194,14 +1218,16 @@
> case ARM::STRH:
> case ARM::STRH_PRE:
> case ARM::STRH_POST:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> }
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> switch (Inst.getOpcode()) {
> case ARM::STRD:
> case ARM::STRD_PRE:
> @@ -1209,7 +1235,8 @@
> case ARM::LDRD:
> case ARM::LDRD_PRE:
> case ARM::LDRD_POST:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1232,31 +1259,35 @@
> case ARM::LDRSB_POST:
> case ARM::LDRHTr:
> case ARM::LDRSBTr:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> }
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> if (type) {
> Inst.addOperand(MCOperand::CreateReg(0));
> Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
> } else {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(U));
> }
>
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeRFEInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned mode = fieldFromInstruction32(Insn, 23, 2);
> @@ -1277,15 +1308,16 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(mode));
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus
> DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst
> &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> @@ -1355,22 +1387,26 @@
> return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail; // Tied
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail; // Tied
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeCPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction32(Insn, 18, 2);
> unsigned M = fieldFromInstruction32(Insn, 17, 1);
> unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
> unsigned mode = fieldFromInstruction32(Insn, 0, 5);
>
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> // imod == '01' --> UNPREDICTABLE
> // NOTE: Even though this is technically UNPREDICTABLE, we choose to
> @@ -1403,14 +1439,14 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2CPSInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction32(Insn, 9, 2);
> unsigned M = fieldFromInstruction32(Insn, 8, 1);
> unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
> unsigned mode = fieldFromInstruction32(Insn, 0, 5);
>
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> // imod == '01' --> UNPREDICTABLE
> // NOTE: Even though this is technically UNPREDICTABLE, we choose to
> @@ -1444,9 +1480,9 @@
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeSMLAInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
> @@ -1457,25 +1493,31 @@
> if (pred == 0xF)
> return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
>
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus
> DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned add = fieldFromInstruction32(Val, 12, 1);
> unsigned imm = fieldFromInstruction32(Val, 0, 12);
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> if (!add) imm *= -1;
> if (imm == 0 && !add) imm = INT32_MIN;
> @@ -1484,15 +1526,16 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeAddrMode5Operand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned U = fieldFromInstruction32(Val, 8, 1);
> unsigned imm = fieldFromInstruction32(Val, 0, 8);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> if (U)
> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
> imm)));
> @@ -1502,15 +1545,15 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeAddrMode7Operand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder)
> {
> return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
> @@ -1523,26 +1566,28 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeVCVTImmOperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(64 - Val));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeAddrMode6Operand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned align = fieldFromInstruction32(Val, 4, 2);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> if (!align)
> Inst.addOperand(MCOperand::CreateImm(0));
> else
> @@ -1551,9 +1596,9 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVLDInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -1563,7 +1608,8 @@
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
>
> // First output register
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> // Second output register
> switch (Inst.getOpcode()) {
> @@ -1615,7 +1661,8 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VLD2b8:
> case ARM::VLD2b16:
> @@ -1635,7 +1682,8 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> default:
> break;
> }
> @@ -1676,7 +1724,8 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VLD3q8:
> case ARM::VLD3q16:
> @@ -1690,7 +1739,8 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1718,7 +1768,8 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VLD4q8:
> case ARM::VLD4q16:
> @@ -1726,7 +1777,8 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1771,28 +1823,31 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> // AddrMode6 Base (register+alignment)
> - if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> // AddrMode6 Offset (register)
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVSTInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -1840,24 +1895,28 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> }
>
> // AddrMode6 Base (register+alignment)
> - if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> // AddrMode6 Offset (register)
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> // First input register
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> // Second input register
> switch (Inst.getOpcode()) {
> @@ -1909,7 +1968,8 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VST2b8:
> case ARM::VST2b16:
> @@ -1929,7 +1989,8 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -1971,7 +2032,8 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VST3q8:
> case ARM::VST3q16:
> @@ -1985,7 +2047,8 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -2013,7 +2076,8 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VST4q8:
> case ARM::VST4q16:
> @@ -2021,7 +2085,8 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -2030,9 +2095,9 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2044,29 +2109,34 @@
>
> align *= (1 << size);
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> if (regs == 2) {
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> }
> if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2077,27 +2147,32 @@
> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
> align *= 2*size;
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2105,28 +2180,34 @@
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(0));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2149,30 +2230,37 @@
> }
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2184,9 +2272,11 @@
> unsigned Q = fieldFromInstruction32(Insn, 6, 1);
>
> if (Q) {
> - if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else {
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> Inst.addOperand(MCOperand::CreateImm(imm));
> @@ -2196,13 +2286,15 @@
> case ARM::VORRiv2i32:
> case ARM::VBICiv4i16:
> case ARM::VBICiv2i32:
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> case ARM::VORRiv8i16:
> case ARM::VORRiv4i32:
> case ARM::VBICiv8i16:
> case ARM::VBICiv4i32:
> - if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> break;
> default:
> break;
> @@ -2211,9 +2303,9 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void
> *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2221,40 +2313,42 @@
> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
> unsigned size = fieldFromInstruction32(Insn, 18, 2);
>
> - if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(8 << size));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeShiftRight8Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(8 - Val));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeShiftRight16Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(16 - Val));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeShiftRight32Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(32 - Val));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeShiftRight64Imm(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(64 - Val));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeTBLInstruction(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> @@ -2265,21 +2359,25 @@
> unsigned op = fieldFromInstruction32(Insn, 6, 1);
> unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> if (op) {
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail; // Writeback
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail; // Writeback
> }
>
> for (unsigned i = 0; i < length; ++i) {
> - if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address,
> Decoder))) return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address,
> Decoder)))
> + return MCDisassembler::Fail;
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> // The immediate needs to be a fully instantiated float. However, the
> // auto-generated decoder is only able to fill in some of the bits
> @@ -2304,14 +2402,15 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst
> &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t
> Insn,
> uint64_t Address, const void
> *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned dst = fieldFromInstruction16(Insn, 8, 3);
> unsigned imm = fieldFromInstruction16(Insn, 0, 8);
>
> - if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> switch(Inst.getOpcode()) {
> default:
> @@ -2327,58 +2426,61 @@
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbBROperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> unsigned Rm = fieldFromInstruction32(Val, 3, 3);
>
> - if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> unsigned imm = fieldFromInstruction32(Val, 3, 5);
>
> - if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModePC(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(Val << 2));
>
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateImm(Val));
> @@ -2386,24 +2488,26 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 6, 4);
> unsigned Rm = fieldFromInstruction32(Val, 2, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 2);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> switch (Inst.getOpcode()) {
> case ARM::t2PLDs:
> @@ -2412,7 +2516,8 @@
> break;
> default: {
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> }
>
> @@ -2449,12 +2554,13 @@
> unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
> addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
> addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
> - if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> int imm = Val & 0xFF;
> if (!(Val & 0x100)) imm *= -1;
> @@ -2463,20 +2569,22 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder)
> {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 9);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) return
> MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> int imm = Val & 0xFF;
> if (!(Val & 0x100)) imm *= -1;
> @@ -2486,9 +2594,9 @@
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 9);
> @@ -2506,28 +2614,31 @@
> break;
> }
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) return
> MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 12);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddSPImm(llvm::MCInst
> &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imm = fieldFromInstruction16(Insn, 0, 7);
>
> @@ -2538,29 +2649,32 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbAddSPReg(llvm::MCInst
> &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> if (Inst.getOpcode() == ARM::tADDrSP) {
> unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
> Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> } else if (Inst.getOpcode() == ARM::tADDspr) {
> unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
>
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst,
> uint16_t Insn,
> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
> unsigned flags = fieldFromInstruction16(Insn, 0, 3);
> @@ -2571,25 +2685,26 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned add = fieldFromInstruction32(Insn, 4, 1);
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(add));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeThumbBLXOffset(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val == 0xA || Val == 0xB)
> return MCDisassembler::Fail;
> @@ -2598,10 +2713,10 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned pred = fieldFromInstruction32(Insn, 22, 4);
> if (pred == 0xE || pred == 0xF) {
> @@ -2630,8 +2745,10 @@
> brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
> brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
>
> - if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
> @@ -2639,7 +2756,7 @@
> // Decode a shifted immediate operand. These basically consist
> // of an 8-bit value, and a 4-bit directive that specifies either
> // a splat operation or a rotation.
> -static MCDisassembler::DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
> if (ctrl == 0) {
> @@ -2670,20 +2787,20 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus
> +static DecodeStatus
> DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder){
> Inst.addOperand(MCOperand::CreateImm(Val << 1));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus
> DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst,
> unsigned Val,
> uint64_t Address, const void
> *Decoder){
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeMemBarrierOption(llvm::MCInst
> &Inst, unsigned Val,
> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned
> Val,
> uint64_t Address, const void *Decoder)
> {
> switch (Val) {
> default:
> @@ -2703,16 +2820,16 @@
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeMSRMask(llvm::MCInst &Inst,
> unsigned Val,
> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (!Val) return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(Val));
> return MCDisassembler::Success;
> }
>
> -static MCDisassembler::DecodeStatus DecodeDoubleRegLoad(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void
> *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -2720,40 +2837,49 @@
>
> if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeDoubleRegStore(llvm::MCInst
> &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned
> Insn,
> uint64_t Address, const void
> *Decoder){
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
> if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2764,17 +2890,21 @@
>
> if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2787,18 +2917,22 @@
> if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
> if (Rm == 0xF) S = MCDisassembler::SoftFail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2809,17 +2943,21 @@
>
> if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> @@ -2830,17 +2968,21 @@
>
> if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2873,28 +3015,33 @@
> align = 4;
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVST1LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2928,27 +3075,31 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2985,30 +3136,37 @@
> break;
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVST2LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3046,28 +3204,33 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3102,33 +3265,42 @@
> break;
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVST3LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3164,29 +3336,35 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
>
> -static MCDisassembler::DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3221,35 +3399,46 @@
> break;
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVST4LN(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3285,29 +3474,36 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> }
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF) {
> if (Rm != 0xD) {
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
> + return MCDisassembler::Fail;
> } else
> Inst.addOperand(MCOperand::CreateReg(0));
> }
>
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
> + return MCDisassembler::Fail;
> Inst.addOperand(MCOperand::CreateImm(index));
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3317,18 +3513,23 @@
> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
> S = MCDisassembler::SoftFail;
>
> - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst,
> unsigned Insn,
> +static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -3338,18 +3539,23 @@
> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
> S = MCDisassembler::SoftFail;
>
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
> return MCDisassembler::Fail;
> - if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
> + return MCDisassembler::Fail;
> + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
> + return MCDisassembler::Fail;
>
> return S;
> }
>
> -static MCDisassembler::DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned
> Insn,
> +static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> - MCDisassembler::DecodeStatus S = MCDisassembler::Success;
> + DecodeStatus S = MCDisassembler::Success;
> unsigned pred = fieldFromInstruction16(Insn, 4, 4);
> // The InstPrinter needs to have the low bit of the predicate in
> // the mask operand to be able to print it properly.
>
>
> _______________________________________________
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> llvm-commits at cs.uiuc.edu
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