[llvm-commits] [llvm] r137830 - in /llvm/trunk: include/llvm/MC/ lib/Target/ARM/Disassembler/ lib/Target/MBlaze/Disassembler/ lib/Target/X86/Disassembler/ test/MC/Disassembler/ARM/ tools/llvm-mc/ utils/TableGen/
Jim Grosbach
grosbach at apple.com
Fri Aug 26 11:56:02 PDT 2011
Sorry for the late comments. I missed this catching these bits the first time around (saw the patch, just missed this aspect).
On Aug 17, 2011, at 10:44 AM, Owen Anderson wrote:
> Author: resistor
> Date: Wed Aug 17 12:44:15 2011
> New Revision: 137830
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137830&view=rev
> Log:
> Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
> Patch by James Molloy.
>
> Modified:
> llvm/trunk/include/llvm/MC/MCDisassembler.h
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h
> llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
> llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
> llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
> llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h
> llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
> llvm/trunk/tools/llvm-mc/Disassembler.cpp
> llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
>
> Modified: llvm/trunk/include/llvm/MC/MCDisassembler.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCDisassembler.h (original)
> +++ llvm/trunk/include/llvm/MC/MCDisassembler.h Wed Aug 17 12:44:15 2011
> @@ -25,6 +25,34 @@
> /// and provides an array of assembly instructions.
> class MCDisassembler {
> public:
> + /// Ternary decode status. Most backends will just use Fail and
> + /// Success, however some have a concept of an instruction with
> + /// understandable semantics but which is architecturally
> + /// incorrect. An example of this is ARM UNPREDICTABLE instructions
> + /// which are disassemblable but cause undefined behaviour.
> + ///
> + /// Because it makes sense to disassemble these instructions, there
> + /// is a "soft fail" failure mode that indicates the MCInst& is
> + /// valid but architecturally incorrect.
> + ///
> + /// The enum numbers are deliberately chosen such that reduction
> + /// from Success->SoftFail ->Fail can be done with a simple
> + /// bitwise-AND:
> + ///
> + /// LEFT & TOP = | Success Unpredictable Fail
> + /// --------------+-----------------------------------
> + /// Success | Success Unpredictable Fail
> + /// Unpredictable | Unpredictable Unpredictable Fail
> + /// Fail | Fail Fail Fail
> + ///
> + /// An easy way of encoding this is as 0b11, 0b01, 0b00 for
> + /// Success, SoftFail, Fail respectively.
> + enum DecodeStatus {
> + Fail = 0,
> + SoftFail = 1,
> + Success = 3
> + };
> +
> /// Constructor - Performs initial setup for the disassembler.
> MCDisassembler() : GetOpInfo(0), DisInfo(0), Ctx(0) {}
>
> @@ -41,8 +69,11 @@
> /// @param address - The address, in the memory space of region, of the first
> /// byte of the instruction.
> /// @param vStream - The stream to print warnings and diagnostic messages on.
> - /// @return - True if the instruction is valid; false otherwise.
> - virtual bool getInstruction(MCInst& instr,
> + /// @return - MCDisassembler::Success if the instruction is valid,
> + /// MCDisassembler::SoftFail if the instruction was
> + /// disassemblable but invalid,
> + /// MCDisassembler::Fail if the instruction was invalid.
> + virtual DecodeStatus getInstruction(MCInst& instr,
> uint64_t& size,
> const MemoryObject ®ion,
> uint64_t address,
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 17 12:44:15 2011
> @@ -24,188 +24,201 @@
> #include "llvm/Support/ErrorHandling.h"
> #include "llvm/Support/raw_ostream.h"
>
> +// Pull DecodeStatus and its enum values into the global namespace.
> +typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
> +#define Success llvm::MCDisassembler::Success
> +#define Unpredictable llvm::MCDisassembler::SoftFail
> +#define Fail llvm::MCDisassembler::Fail
> +
Please don't do this sort of thing (#defines to get around scoping). Reference the names explicitly, including the scoping operators, instead.
> +// Helper macro to perform setwise reduction of the current running status
> +// and another status, and return if the new status is Fail.
> +#define CHECK(S,X) do { \
> + S = (DecodeStatus) ((int)S & (X)); \
It's better to use the enum values directly rather than casting integers like this. The code shouldn't know what the actual values of the enums are.
> + if (S == Fail) return Fail; \
> + } while(0)
> +
Having an early exit buried in a macro obfuscates the code. The way the code previously did this is better. Please change this back or refactor differently.
> // Forward declare these because the autogenerated code will reference them.
> // Definitions are further down.
> -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
> -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder);
>
> -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
>
> -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
>
> -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
> unsigned Insn,
> uint64_t Adddress,
> const void *Decoder);
> -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
>
>
> -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
> -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder);
>
> #include "ARMGenDisassemblerTables.inc"
> @@ -230,15 +243,14 @@
> return instInfoARM;
> }
>
> -
> -bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> - const MemoryObject &Region,
> - uint64_t Address,raw_ostream &os) const {
> +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> + const MemoryObject &Region,
> + uint64_t Address,raw_ostream &os) const {
> uint8_t bytes[4];
>
> // We want to read exactly 4 bytes of data.
> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
> - return false;
> + return Fail;
>
> // Encoded as a small-endian 32-bit word in the stream.
> uint32_t insn = (bytes[3] << 24) |
> @@ -247,10 +259,10 @@
> (bytes[0] << 0);
>
> // Calling the auto-generated decoder function.
> - bool result = decodeARMInstruction32(MI, insn, Address, this);
> - if (result) {
> + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
> + if (result != Fail) {
> Size = 4;
> - return true;
> + return result;
> }
>
> // Instructions that are shared between ARM and Thumb modes.
> @@ -258,53 +270,53 @@
> // fact that we fail to encode a few instructions properly for Thumb.
> MI.clear();
> result = decodeCommonInstruction32(MI, insn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> - return true;
> + return result;
> }
>
> // VFP and NEON instructions, similarly, are shared between ARM
> // and Thumb modes.
> MI.clear();
> result = decodeVFPInstruction32(MI, insn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> - return true;
> + return result;
> }
>
> MI.clear();
> result = decodeNEONDataInstruction32(MI, insn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
> - return true;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
> + return result;
> }
>
> MI.clear();
> result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
> - return true;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
> + return result;
> }
>
> MI.clear();
> result = decodeNEONDupInstruction32(MI, insn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> // Add a fake predicate operand, because we share these instruction
> // definitions with Thumb2 where these instructions are predicable.
> - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
> - return true;
> + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
> + return result;
> }
>
> MI.clear();
>
> - return false;
> + return Fail;
> }
>
> namespace llvm {
> @@ -403,22 +415,21 @@
> }
> }
>
> -
> -bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> - const MemoryObject &Region,
> - uint64_t Address,raw_ostream &os) const {
> +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
> + const MemoryObject &Region,
> + uint64_t Address,raw_ostream &os) const {
> uint8_t bytes[4];
>
> // We want to read exactly 2 bytes of data.
> if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
> - return false;
> + return Fail;
>
> uint16_t insn16 = (bytes[1] << 8) | bytes[0];
> - bool result = decodeThumbInstruction16(MI, insn16, Address, this);
> - if (result) {
> + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
> + if (result != Fail) {
> Size = 2;
> AddThumbPredicate(MI);
> - return true;
> + return result;
> }
>
> MI.clear();
> @@ -428,12 +439,12 @@
> bool InITBlock = !ITBlock.empty();
> AddThumbPredicate(MI);
> AddThumb1SBit(MI, InITBlock);
> - return true;
> + return result;
> }
>
> MI.clear();
> result = decodeThumb2Instruction16(MI, insn16, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 2;
> AddThumbPredicate(MI);
>
> @@ -456,12 +467,12 @@
> ITBlock.push_back(firstcond);
> }
>
> - return true;
> + return result;
> }
>
> // We want to read exactly 4 bytes of data.
> if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
> - return false;
> + return Fail;
>
> uint32_t insn32 = (bytes[3] << 8) |
> (bytes[2] << 0) |
> @@ -469,44 +480,44 @@
> (bytes[0] << 16);
> MI.clear();
> result = decodeThumbInstruction32(MI, insn32, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> bool InITBlock = ITBlock.size();
> AddThumbPredicate(MI);
> AddThumb1SBit(MI, InITBlock);
> - return true;
> + return result;
> }
>
> MI.clear();
> result = decodeThumb2Instruction32(MI, insn32, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> - return true;
> + return result;
> }
>
> MI.clear();
> result = decodeCommonInstruction32(MI, insn32, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> - return true;
> + return result;
> }
>
> MI.clear();
> result = decodeVFPInstruction32(MI, insn32, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> UpdateThumbVFPPredicate(MI);
> - return true;
> + return result;
> }
>
> MI.clear();
> result = decodeNEONDupInstruction32(MI, insn32, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> - return true;
> + return result;
> }
>
> if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
> @@ -515,10 +526,10 @@
> NEONLdStInsn &= 0xF0FFFFFF;
> NEONLdStInsn |= 0x04000000;
> result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> - return true;
> + return result;
> }
> }
>
> @@ -529,14 +540,14 @@
> NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
> NEONDataInsn |= 0x12000000; // Set bits 28 and 25
> result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
> - if (result) {
> + if (result != Fail) {
> Size = 4;
> AddThumbPredicate(MI);
> - return true;
> + return result;
> }
> }
>
> - return false;
> + return Fail;
> }
>
>
> @@ -554,30 +565,30 @@
> ARM::R12, ARM::SP, ARM::LR, ARM::PC
> };
>
> -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 15)
> - return false;
> + return Fail;
>
> unsigned Register = GPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return true;
> + return Success;
> }
>
> -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> - if (RegNo == 15) return false;
> + if (RegNo == 15) return Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 7)
> - return false;
> + return Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> unsigned Register = 0;
> switch (RegNo) {
> @@ -600,16 +611,16 @@
> Register = ARM::R12;
> break;
> default:
> - return false;
> + return Fail;
> }
>
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return true;
> + return Success;
> }
>
> -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> - if (RegNo == 13 || RegNo == 15) return false;
> + if (RegNo == 13 || RegNo == 15) return Fail;
> return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> @@ -624,14 +635,14 @@
> ARM::S28, ARM::S29, ARM::S30, ARM::S31
> };
>
> -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 31)
> - return false;
> + return Fail;
>
> unsigned Register = SPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return true;
> + return Success;
> }
>
> static const unsigned DPRDecoderTable[] = {
> @@ -645,27 +656,27 @@
> ARM::D28, ARM::D29, ARM::D30, ARM::D31
> };
>
> -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 31)
> - return false;
> + return Fail;
>
> unsigned Register = DPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return true;
> + return Success;
> }
>
> -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 7)
> - return false;
> + return Fail;
> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 15)
> - return false;
> + return Fail;
> return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
> }
>
> @@ -677,65 +688,66 @@
> };
>
>
> -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
> uint64_t Address, const void *Decoder) {
> if (RegNo > 31)
> - return false;
> + return Fail;
> RegNo >>= 1;
>
> unsigned Register = QPRDecoderTable[RegNo];
> Inst.addOperand(MCOperand::CreateReg(Register));
> - return true;
> + return Success;
> }
>
> -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - if (Val == 0xF) return false;
> + if (Val == 0xF) return Fail;
> // AL predicate is not allowed on Thumb1 branches.
> if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
> - return false;
> + return Fail;
> Inst.addOperand(MCOperand::CreateImm(Val));
> if (Val == ARMCC::AL) {
> Inst.addOperand(MCOperand::CreateReg(0));
> } else
> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> - return true;
> + return Success;
> }
>
> -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val)
> Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
> else
> Inst.addOperand(MCOperand::CreateReg(0));
> - return true;
> + return Success;
> }
>
> -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> uint32_t imm = Val & 0xFF;
> uint32_t rot = (Val & 0xF00) >> 7;
> uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
> Inst.addOperand(MCOperand::CreateImm(rot_imm));
> - return true;
> + return Success;
> }
>
> -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Val <<= 2;
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> unsigned imm = fieldFromInstruction32(Val, 7, 5);
>
> // Register-immediate
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
>
> ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> switch (type) {
> @@ -759,19 +771,20 @@
> unsigned Op = Shift | (imm << 3);
> Inst.addOperand(MCOperand::CreateImm(Op));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
>
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> unsigned Rs = fieldFromInstruction32(Val, 8, 4);
>
> // Register-register
> - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
> - if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
>
> ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
> switch (type) {
> @@ -791,49 +804,55 @@
>
> Inst.addOperand(MCOperand::CreateImm(Shift));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> // Empty register lists are not allowed.
> - if (CountPopulation_32(Val) == 0) return false;
> + if (CountPopulation_32(Val) == 0) return Fail;
> for (unsigned i = 0; i < 16; ++i) {
> if (Val & (1 << i)) {
> - if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
> }
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> unsigned regs = Val & 0xFF;
>
> - if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false;
> + CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
> for (unsigned i = 0; i < (regs - 1); ++i) {
> - if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false;
> + CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Vd = fieldFromInstruction32(Val, 8, 4);
> unsigned regs = (Val & 0xFF) / 2;
>
> - if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
> for (unsigned i = 0; i < (regs - 1); ++i) {
> - if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> // This operand encodes a mask of contiguous zeros between a specified MSB
> // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
> @@ -845,11 +864,13 @@
> uint32_t msb_mask = (1 << (msb+1)) - 1;
> uint32_t lsb_mask = (1 << lsb) - 1;
> Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
> unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
> @@ -875,7 +896,7 @@
> case ARM::STCL_POST:
> case ARM::STCL_OPTION:
> if (coproc == 0xA || coproc == 0xB)
> - return false;
> + return Fail;
> break;
> default:
> break;
> @@ -883,7 +904,7 @@
>
> Inst.addOperand(MCOperand::CreateImm(coproc));
> Inst.addOperand(MCOperand::CreateImm(CRd));
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> switch (Inst.getOpcode()) {
> case ARM::LDC_OPTION:
> case ARM::LDCL_OPTION:
> @@ -952,17 +973,19 @@
> case ARM::STCL_PRE:
> case ARM::STCL_POST:
> case ARM::STCL_OPTION:
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> break;
> default:
> break;
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -982,13 +1005,13 @@
> case ARM::STRT_POST_IMM:
> case ARM::STRBT_POST_REG:
> case ARM::STRBT_POST_IMM:
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> break;
> default:
> break;
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
>
> // On loads, the writeback operand comes after Rt.
> switch (Inst.getOpcode()) {
> @@ -1002,14 +1025,13 @@
> case ARM::LDRBT_POST_IMM:
> case ARM::LDRT_POST_REG:
> case ARM::LDRT_POST_IMM:
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> break;
> default:
> break;
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
>
> ARM_AM::AddrOpc Op = ARM_AM::add;
> if (!fieldFromInstruction32(Insn, 23, 1))
> @@ -1022,10 +1044,10 @@
> else if (!P && writeback)
> idx_mode = ARMII::IndexModePost;
>
> - if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE
> + if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
>
> if (reg) {
> - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
> ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
> switch( fieldFromInstruction32(Insn, 5, 2)) {
> case 0:
> @@ -1041,7 +1063,7 @@
> Opc = ARM_AM::ror;
> break;
> default:
> - return false;
> + return Fail;
> }
> unsigned amt = fieldFromInstruction32(Insn, 7, 5);
> unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
> @@ -1053,13 +1075,15 @@
> Inst.addOperand(MCOperand::CreateImm(tmp));
> }
>
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned type = fieldFromInstruction32(Val, 5, 2);
> @@ -1082,8 +1106,8 @@
> break;
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> unsigned shift;
> if (U)
> shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
> @@ -1091,11 +1115,13 @@
> shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
> Inst.addOperand(MCOperand::CreateImm(shift));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> @@ -1116,7 +1142,7 @@
> case ARM::LDRD:
> case ARM::LDRD_PRE:
> case ARM::LDRD_POST:
> - if (Rt & 0x1) return false;
> + if (Rt & 0x1) return Fail;
> break;
> default:
> break;
> @@ -1136,16 +1162,14 @@
> case ARM::STRH:
> case ARM::STRH_PRE:
> case ARM::STRH_POST:
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> break;
> default:
> break;
> }
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> switch (Inst.getOpcode()) {
> case ARM::STRD:
> case ARM::STRD_PRE:
> @@ -1153,8 +1177,7 @@
> case ARM::LDRD:
> case ARM::LDRD_PRE:
> case ARM::LDRD_POST:
> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
> break;
> default:
> break;
> @@ -1177,33 +1200,32 @@
> case ARM::LDRSB_POST:
> case ARM::LDRHTr:
> case ARM::LDRSBTr:
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> break;
> default:
> break;
> }
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
>
> if (type) {
> Inst.addOperand(MCOperand::CreateReg(0));
> Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
> } else {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(U));
> }
>
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned mode = fieldFromInstruction32(Insn, 23, 2);
>
> @@ -1223,14 +1245,16 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(mode));
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
> +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
> unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
> @@ -1265,16 +1289,15 @@
> return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
> - !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied
> - !DecodePredicateOperand(Inst, pred, Address, Decoder) ||
> - !DecodeRegListOperand(Inst, reglist, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
> + CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction32(Insn, 18, 2);
> unsigned M = fieldFromInstruction32(Insn, 17, 1);
> @@ -1282,30 +1305,32 @@
> unsigned mode = fieldFromInstruction32(Insn, 0, 5);
>
> // imod == '01' --> UNPREDICTABLE
> - if (imod == 1) return false;
> + if (imod == 1) return Fail;
>
> if (M && mode && imod && iflags) {
> Inst.setOpcode(ARM::CPS3p);
> Inst.addOperand(MCOperand::CreateImm(imod));
> Inst.addOperand(MCOperand::CreateImm(iflags));
> Inst.addOperand(MCOperand::CreateImm(mode));
> - return true;
> + return Success;
> } else if (!mode && !M) {
> Inst.setOpcode(ARM::CPS2p);
> Inst.addOperand(MCOperand::CreateImm(imod));
> Inst.addOperand(MCOperand::CreateImm(iflags));
> - return true;
> + return Success;
> } else if (!imod && !iflags && M) {
> Inst.setOpcode(ARM::CPS1p);
> Inst.addOperand(MCOperand::CreateImm(mode));
> - return true;
> + return Success;
> }
>
> - return false;
> + return Fail;
> }
>
> -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
> @@ -1315,57 +1340,60 @@
> if (pred == 0xF)
> return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
>
> - if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) ||
> - !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) ||
> - !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) ||
> - !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
> + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
>
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned add = fieldFromInstruction32(Val, 12, 1);
> unsigned imm = fieldFromInstruction32(Val, 0, 12);
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
>
> if (!add) imm *= -1;
> if (imm == 0 && !add) imm = INT32_MIN;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned U = fieldFromInstruction32(Val, 8, 1);
> unsigned imm = fieldFromInstruction32(Val, 0, 8);
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
>
> if (U)
> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
> else
> Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
> }
>
> -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
> unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
>
> @@ -1373,39 +1401,42 @@
> Inst.setOpcode(ARM::BLXi);
> imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
> - return true;
> + return S;
> }
>
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(64 - Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rm = fieldFromInstruction32(Val, 0, 4);
> unsigned align = fieldFromInstruction32(Val, 4, 2);
>
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> if (!align)
> Inst.addOperand(MCOperand::CreateImm(0));
> else
> Inst.addOperand(MCOperand::CreateImm(4 << align));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned wb = fieldFromInstruction32(Insn, 16, 4);
> @@ -1414,7 +1445,7 @@
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
>
> // First output register
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
>
> // Second output register
> switch (Inst.getOpcode()) {
> @@ -1466,7 +1497,7 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
> break;
> case ARM::VLD2b8:
> case ARM::VLD2b16:
> @@ -1486,7 +1517,7 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> default:
> break;
> }
> @@ -1527,7 +1558,7 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> break;
> case ARM::VLD3q8:
> case ARM::VLD3q16:
> @@ -1541,7 +1572,7 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
> break;
> default:
> break;
> @@ -1569,7 +1600,7 @@
> case ARM::VLD4d8_UPD:
> case ARM::VLD4d16_UPD:
> case ARM::VLD4d32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
> break;
> case ARM::VLD4q8:
> case ARM::VLD4q16:
> @@ -1577,7 +1608,7 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
> break;
> default:
> break;
> @@ -1622,28 +1653,29 @@
> case ARM::VLD4q8_UPD:
> case ARM::VLD4q16_UPD:
> case ARM::VLD4q32_UPD:
> - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
> break;
> default:
> break;
> }
>
> // AddrMode6 Base (register+alignment)
> - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
>
> // AddrMode6 Offset (register)
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned wb = fieldFromInstruction32(Insn, 16, 4);
> @@ -1690,25 +1722,24 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
> break;
> default:
> break;
> }
>
> // AddrMode6 Base (register+alignment)
> - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
>
> // AddrMode6 Offset (register)
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> // First input register
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
>
> // Second input register
> switch (Inst.getOpcode()) {
> @@ -1760,7 +1791,7 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
> break;
> case ARM::VST2b8:
> case ARM::VST2b16:
> @@ -1780,7 +1811,7 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> break;
> default:
> break;
> @@ -1822,7 +1853,7 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
> break;
> case ARM::VST3q8:
> case ARM::VST3q16:
> @@ -1836,7 +1867,7 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
> break;
> default:
> break;
> @@ -1864,7 +1895,7 @@
> case ARM::VST4d8_UPD:
> case ARM::VST4d16_UPD:
> case ARM::VST4d32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
> break;
> case ARM::VST4q8:
> case ARM::VST4q16:
> @@ -1872,17 +1903,19 @@
> case ARM::VST4q8_UPD:
> case ARM::VST4q16_UPD:
> case ARM::VST4q32_UPD:
> - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
> break;
> default:
> break;
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -1893,28 +1926,30 @@
>
> align *= (1 << size);
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> if (regs == 2) {
> - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
> }
> if (Rm == 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -1924,54 +1959,57 @@
> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
> align *= 2*size;
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
> if (Rm == 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) ||
> - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) ||
> - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))
> - return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
> if (Rm == 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(0));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -1993,29 +2031,30 @@
> }
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) ||
> - !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) ||
> - !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) ||
> - !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))
> - return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
> if (Rm == 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
>
> if (Rm == 0xD)
> Inst.addOperand(MCOperand::CreateReg(0));
> else if (Rm != 0xF) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned imm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2026,9 +2065,9 @@
> unsigned Q = fieldFromInstruction32(Insn, 6, 1);
>
> if (Q) {
> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
> } else {
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> }
>
> Inst.addOperand(MCOperand::CreateImm(imm));
> @@ -2038,62 +2077,66 @@
> case ARM::VORRiv2i32:
> case ARM::VBICiv4i16:
> case ARM::VBICiv2i32:
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> break;
> case ARM::VORRiv8i16:
> case ARM::VORRiv4i32:
> case ARM::VBICiv8i16:
> case ARM::VBICiv4i32:
> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
> break;
> default:
> break;
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
> unsigned size = fieldFromInstruction32(Insn, 18, 2);
>
> - if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(8 << size));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(8 - Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(16 - Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(32 - Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(64 - Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -2103,21 +2146,21 @@
> unsigned op = fieldFromInstruction32(Insn, 6, 1);
> unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> if (op) {
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
> }
>
> for (unsigned i = 0; i < length; ++i) {
> - if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> // The immediate needs to be a fully instantiated float. However, the
> // auto-generated decoder is only able to fill in some of the bits
> @@ -2139,102 +2182,110 @@
> fp_conv.integer |= (~b & 0x1) << 30;
>
> Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned dst = fieldFromInstruction16(Insn, 8, 3);
> unsigned imm = fieldFromInstruction16(Insn, 0, 8);
>
> - if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false;
> + CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
>
> if (Inst.getOpcode() == ARM::tADR)
> Inst.addOperand(MCOperand::CreateReg(ARM::PC));
> else if (Inst.getOpcode() == ARM::tADDrSPi)
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> else
> - return false;
> + return Fail;
>
> Inst.addOperand(MCOperand::CreateImm(imm));
> - return true;
> + return S;
> }
>
> -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> unsigned Rm = fieldFromInstruction32(Val, 3, 3);
>
> - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) ||
> - !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 0, 3);
> unsigned imm = fieldFromInstruction32(Val, 3, 5);
>
> - if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(Val << 2));
>
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateImm(Val << 2));
>
> - return true;
> + return Success;
> }
>
> -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 6, 4);
> unsigned Rm = fieldFromInstruction32(Val, 2, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 2);
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
> - !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> if (Inst.getOpcode() != ARM::t2PLDs) {
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> }
>
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> @@ -2257,57 +2308,60 @@
> Inst.addOperand(MCOperand::CreateReg(ARM::PC));
> break;
> default:
> - return false;
> + return Fail;
> }
>
> int imm = fieldFromInstruction32(Insn, 0, 12);
> if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return S;
> }
>
> unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
> addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
> addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
> - DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder);
> + CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> int imm = Val & 0xFF;
> if (!(Val & 0x100)) imm *= -1;
> Inst.addOperand(MCOperand::CreateImm(imm << 2));
>
> - return true;
> + return Success;
> }
>
> -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 9);
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
> - !DecodeT2Imm8S4(Inst, imm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> int imm = Val & 0xFF;
> if (!(Val & 0x100)) imm *= -1;
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return Success;
> }
>
>
> -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 9, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 9);
>
> @@ -2324,27 +2378,28 @@
> break;
> }
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
> - !DecodeT2Imm8(Inst, imm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Val, 13, 4);
> unsigned imm = fieldFromInstruction32(Val, 0, 12);
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imm = fieldFromInstruction16(Insn, 0, 7);
>
> @@ -2352,30 +2407,32 @@
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateImm(imm));
>
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> if (Inst.getOpcode() == ARM::tADDrSP) {
> unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
> Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
>
> - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> - if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
> } else if (Inst.getOpcode() == ARM::tADDspr) {
> unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
>
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - return true;
> + return S;
> }
>
> -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
> uint64_t Address, const void *Decoder) {
> unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
> unsigned flags = fieldFromInstruction16(Insn, 0, 3);
> @@ -2383,52 +2440,55 @@
> Inst.addOperand(MCOperand::CreateImm(imod));
> Inst.addOperand(MCOperand::CreateImm(flags));
>
> - return true;
> + return Success;
> }
>
> -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned add = fieldFromInstruction32(Insn, 4, 1);
>
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
> Inst.addOperand(MCOperand::CreateImm(add));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val == 0xA || Val == 0xB)
> - return false;
> + return Fail;
>
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> if (Val == 0)
> Inst.addOperand(MCOperand::CreateImm(32));
> else
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned pred = fieldFromInstruction32(Insn, 22, 4);
> if (pred == 0xE || pred == 0xF) {
> unsigned opc = fieldFromInstruction32(Insn, 4, 2);
> switch (opc) {
> default:
> - return false;
> + return Fail;
> case 0:
> Inst.setOpcode(ARM::t2DSB);
> break;
> @@ -2437,7 +2497,7 @@
> break;
> case 2:
> Inst.setOpcode(ARM::t2ISB);
> - return true;
> + return Success;
> }
>
> unsigned imm = fieldFromInstruction32(Insn, 0, 4);
> @@ -2450,17 +2510,16 @@
> brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
> brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
>
> - if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) ||
> - !DecodePredicateOperand(Inst, pred, Address, Decoder))
> - return false;
> + CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> // Decode a shifted immediate operand. These basically consist
> // of an 8-bit value, and a 4-bit directive that specifies either
> // a splat operation or a rotation.
> -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
> if (ctrl == 0) {
> @@ -2488,26 +2547,26 @@
> Inst.addOperand(MCOperand::CreateImm(imm));
> }
>
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder){
> Inst.addOperand(MCOperand::CreateImm(Val << 1));
> - return true;
> + return Success;
> }
>
> -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder){
> Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
> - return true;
> + return Success;
> }
>
> -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> switch (Val) {
> default:
> - return false;
> + return Fail;
> case 0xF: // SY
> case 0xE: // ST
> case 0xB: // ISH
> @@ -2520,55 +2579,61 @@
> }
>
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
> +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
> uint64_t Address, const void *Decoder) {
> - if (!Val) return false;
> + if (!Val) return Fail;
> Inst.addOperand(MCOperand::CreateImm(Val));
> - return true;
> + return Success;
> }
>
> -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
>
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
>
> - if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
> - if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;
> + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
> + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
>
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned imm = fieldFromInstruction32(Insn, 0, 12);
> @@ -2576,18 +2641,20 @@
> imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
> + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
> - if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false;
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
> unsigned imm = fieldFromInstruction32(Insn, 0, 12);
> @@ -2595,18 +2662,20 @@
> imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>
> - if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
> + if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
>
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
> - if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false;
> - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
> + CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
> + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2617,47 +2686,47 @@
> unsigned index = 0;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 6, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 2) != 0)
> align = 4;
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2668,47 +2737,47 @@
> unsigned index = 0;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 6, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 2) != 0)
> align = 4;
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2720,7 +2789,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> index = fieldFromInstruction32(Insn, 5, 3);
> if (fieldFromInstruction32(Insn, 4, 1))
> @@ -2735,7 +2804,7 @@
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 1) != 0)
> align = 8;
> @@ -2744,28 +2813,28 @@
> break;
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2777,7 +2846,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> index = fieldFromInstruction32(Insn, 5, 3);
> if (fieldFromInstruction32(Insn, 4, 1))
> @@ -2792,7 +2861,7 @@
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 5, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 4, 1) != 0)
> align = 8;
> @@ -2802,26 +2871,26 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2833,53 +2902,53 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 5, 1))
> inc = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 4, 2))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 6, 1))
> inc = 2;
> break;
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
>
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2891,22 +2960,22 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 5, 3);
> break;
> case 1:
> if (fieldFromInstruction32(Insn, 4, 1))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 6, 2);
> if (fieldFromInstruction32(Insn, 5, 1))
> inc = 2;
> break;
> case 2:
> if (fieldFromInstruction32(Insn, 4, 2))
> - return false; // UNDEFINED
> + return Fail; // UNDEFINED
> index = fieldFromInstruction32(Insn, 7, 1);
> if (fieldFromInstruction32(Insn, 6, 1))
> inc = 2;
> @@ -2914,27 +2983,27 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
>
> -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -2946,7 +3015,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 4;
> @@ -2968,33 +3037,33 @@
> break;
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
>
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
> -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
> uint64_t Address, const void *Decoder) {
> + DecodeStatus S = Success;
> +
> unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
> unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
> unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
> @@ -3006,7 +3075,7 @@
> unsigned inc = 1;
> switch (size) {
> default:
> - return false;
> + return Fail;
> case 0:
> if (fieldFromInstruction32(Insn, 4, 1))
> align = 4;
> @@ -3029,22 +3098,20 @@
> }
>
> if (Rm != 0xF) { // Writeback
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> }
> - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(align));
> if (Rm != 0xF && Rm != 0xD) {
> - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
> - return false;
> + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
> }
>
> - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false;
> - if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false;
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
> + CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
> Inst.addOperand(MCOperand::CreateImm(index));
>
> - return true;
> + return S;
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.h Wed Aug 17 12:44:15 2011
> @@ -40,11 +40,11 @@
> }
>
> /// getInstruction - See MCDisassembler.
> - bool getInstruction(MCInst &instr,
> - uint64_t &size,
> - const MemoryObject ®ion,
> - uint64_t address,
> - raw_ostream &vStream) const;
> + DecodeStatus getInstruction(MCInst &instr,
> + uint64_t &size,
> + const MemoryObject ®ion,
> + uint64_t address,
> + raw_ostream &vStream) const;
>
> /// getEDInfo - See MCDisassembler.
> EDInstInfo *getEDInfo() const;
> @@ -64,11 +64,11 @@
> }
>
> /// getInstruction - See MCDisassembler.
> - bool getInstruction(MCInst &instr,
> - uint64_t &size,
> - const MemoryObject ®ion,
> - uint64_t address,
> - raw_ostream &vStream) const;
> + DecodeStatus getInstruction(MCInst &instr,
> + uint64_t &size,
> + const MemoryObject ®ion,
> + uint64_t address,
> + raw_ostream &vStream) const;
>
> /// getEDInfo - See MCDisassembler.
> EDInstInfo *getEDInfo() const;
>
> Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Wed Aug 17 12:44:15 2011
> @@ -493,7 +493,7 @@
> // Public interface for the disassembler
> //
>
> -bool MBlazeDisassembler::getInstruction(MCInst &instr,
> +MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr,
> uint64_t &size,
> const MemoryObject ®ion,
> uint64_t address,
> @@ -508,7 +508,7 @@
>
> // We want to read exactly 4 bytes of data.
> if (region.readBytes(address, 4, (uint8_t*)bytes, &read) == -1 || read < 4)
> - return false;
> + return Fail;
>
> // Encoded as a big-endian 32-bit word in the stream.
> insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0);
> @@ -517,7 +517,7 @@
> // that it is a valid instruction.
> unsigned opcode = getOPCODE(insn);
> if (opcode == UNSUPPORTED)
> - return false;
> + return Fail;
>
> instr.setOpcode(opcode);
>
> @@ -529,11 +529,11 @@
> uint64_t tsFlags = MBlazeInsts[opcode].TSFlags;
> switch ((tsFlags & MBlazeII::FormMask)) {
> default:
> - return false;
> + return Fail;
>
> case MBlazeII::FRRRR:
> if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RB));
> instr.addOperand(MCOperand::CreateReg(RA));
> @@ -541,7 +541,7 @@
>
> case MBlazeII::FRRR:
> if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RA));
> instr.addOperand(MCOperand::CreateReg(RB));
> @@ -550,23 +550,23 @@
> case MBlazeII::FRI:
> switch (opcode) {
> default:
> - return false;
> + return Fail;
> case MBlaze::MFS:
> if (RD == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
> break;
> case MBlaze::MTS:
> if (RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
> instr.addOperand(MCOperand::CreateReg(RA));
> break;
> case MBlaze::MSRSET:
> case MBlaze::MSRCLR:
> if (RD == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateImm(insn&0x7FFF));
> break;
> @@ -575,7 +575,7 @@
>
> case MBlazeII::FRRI:
> if (RD == UNSUPPORTED || RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RA));
> switch (opcode) {
> @@ -592,35 +592,35 @@
>
> case MBlazeII::FCRR:
> if (RA == UNSUPPORTED || RB == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RA));
> instr.addOperand(MCOperand::CreateReg(RB));
> break;
>
> case MBlazeII::FCRI:
> if (RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RA));
> instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
> break;
>
> case MBlazeII::FRCR:
> if (RD == UNSUPPORTED || RB == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RB));
> break;
>
> case MBlazeII::FRCI:
> if (RD == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
> break;
>
> case MBlazeII::FCCR:
> if (RB == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RB));
> break;
>
> @@ -630,7 +630,7 @@
>
> case MBlazeII::FRRCI:
> if (RD == UNSUPPORTED || RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RA));
> instr.addOperand(MCOperand::CreateImm(getSHT(insn)));
> @@ -638,35 +638,35 @@
>
> case MBlazeII::FRRC:
> if (RD == UNSUPPORTED || RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RA));
> break;
>
> case MBlazeII::FRCX:
> if (RD == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
> break;
>
> case MBlazeII::FRCS:
> if (RD == UNSUPPORTED || RS == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateReg(RS));
> break;
>
> case MBlazeII::FCRCS:
> if (RS == UNSUPPORTED || RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RS));
> instr.addOperand(MCOperand::CreateReg(RA));
> break;
>
> case MBlazeII::FCRCX:
> if (RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RA));
> instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
> break;
> @@ -677,13 +677,13 @@
>
> case MBlazeII::FCR:
> if (RB == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RB));
> break;
>
> case MBlazeII::FRIR:
> if (RD == UNSUPPORTED || RA == UNSUPPORTED)
> - return false;
> + return Fail;
> instr.addOperand(MCOperand::CreateReg(RD));
> instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
> instr.addOperand(MCOperand::CreateReg(RA));
> @@ -693,7 +693,7 @@
> // We always consume 4 bytes of data on success
> size = 4;
>
> - return true;
> + return Success;
> }
>
> static MCDisassembler *createMBlazeDisassembler(const Target &T) {
>
> Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h (original)
> +++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h Wed Aug 17 12:44:15 2011
> @@ -40,7 +40,7 @@
> }
>
> /// getInstruction - See MCDisassembler.
> - bool getInstruction(MCInst &instr,
> + MCDisassembler::DecodeStatus getInstruction(MCInst &instr,
> uint64_t &size,
> const MemoryObject ®ion,
> uint64_t address,
>
> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed Aug 17 12:44:15 2011
> @@ -106,11 +106,12 @@
> // Public interface for the disassembler
> //
>
> -bool X86GenericDisassembler::getInstruction(MCInst &instr,
> - uint64_t &size,
> - const MemoryObject ®ion,
> - uint64_t address,
> - raw_ostream &vStream) const {
> +MCDisassembler::DecodeStatus
> +X86GenericDisassembler::getInstruction(MCInst &instr,
> + uint64_t &size,
> + const MemoryObject ®ion,
> + uint64_t address,
> + raw_ostream &vStream) const {
> InternalInstruction internalInstr;
>
> int ret = decodeInstruction(&internalInstr,
> @@ -123,11 +124,11 @@
>
> if (ret) {
> size = internalInstr.readerCursor - address;
> - return false;
> + return Fail;
> }
> else {
> size = internalInstr.length;
> - return !translateInstruction(instr, internalInstr);
> + return (!translateInstruction(instr, internalInstr)) ? Success : Fail;
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h (original)
> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.h Wed Aug 17 12:44:15 2011
> @@ -112,11 +112,11 @@
> ~X86GenericDisassembler();
>
> /// getInstruction - See MCDisassembler.
> - bool getInstruction(MCInst &instr,
> - uint64_t &size,
> - const MemoryObject ®ion,
> - uint64_t address,
> - raw_ostream &vStream) const;
> + DecodeStatus getInstruction(MCInst &instr,
> + uint64_t &size,
> + const MemoryObject ®ion,
> + uint64_t address,
> + raw_ostream &vStream) const;
>
> /// getEDInfo - See MCDisassembler.
> EDInstInfo *getEDInfo() const;
>
> Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt Wed Aug 17 12:44:15 2011
> @@ -1,4 +1,4 @@
> -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
> +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}
>
> # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
> # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
>
> Modified: llvm/trunk/tools/llvm-mc/Disassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/Disassembler.cpp?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-mc/Disassembler.cpp (original)
> +++ llvm/trunk/tools/llvm-mc/Disassembler.cpp Wed Aug 17 12:44:15 2011
> @@ -65,15 +65,26 @@
> for (Index = 0; Index < Bytes.size(); Index += Size) {
> MCInst Inst;
>
> - if (DisAsm.getInstruction(Inst, Size, memoryObject, Index,
> - /*REMOVE*/ nulls())) {
> - Printer.printInst(&Inst, Out);
> - Out << "\n";
> - } else {
> + MCDisassembler::DecodeStatus S;
> + S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
> + /*REMOVE*/ nulls());
> + switch (S) {
Changing this to a switch statement is good. The C bindings in MCDisasembler.cpp and EDDisassembler.cpp need to be changed, too, though. They're still doing "!Disasm->getInstruction()" type constructs.
> + case MCDisassembler::Fail:
> SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
> "invalid instruction encoding", "warning");
> if (Size == 0)
> Size = 1; // skip illegible bytes
> + break;
> +
> + case MCDisassembler::SoftFail:
> + SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
> + "potentially undefined instruction encoding", "warning");
> + // Fall through
> +
> + case MCDisassembler::Success:
> + Printer.printInst(&Inst, Out);
> + Out << "\n";
> + break;
> }
> }
>
>
> Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Wed Aug 17 12:44:15 2011
> @@ -128,5 +128,15 @@
> return;
> }
>
> + // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses.
> + if (Target.getName() == "ARM" ||
> + Target.getName() == "Thumb") {
> + FixedLenDecoderEmitter(Records,
> + "CHECK(S, ", ");",
> + "S", "Fail",
> + "DecodeStatus S = Success;\n(void)S;").run(OS);
> + return;
> + }
> +
> FixedLenDecoderEmitter(Records).run(OS);
> }
>
> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed Aug 17 12:44:15 2011
> @@ -238,19 +238,24 @@
> // Width of instructions
> unsigned BitWidth;
>
> + // Parent emitter
> + const FixedLenDecoderEmitter *Emitter;
> +
> public:
> FilterChooser(const FilterChooser &FC) :
> AllInstructions(FC.AllInstructions), Opcodes(FC.Opcodes),
> Operands(FC.Operands), Filters(FC.Filters),
> FilterBitValues(FC.FilterBitValues), Parent(FC.Parent),
> - BestIndex(FC.BestIndex), BitWidth(FC.BitWidth) { }
> + BestIndex(FC.BestIndex), BitWidth(FC.BitWidth),
> + Emitter(FC.Emitter) { }
>
> FilterChooser(const std::vector<const CodeGenInstruction*> &Insts,
> const std::vector<unsigned> &IDs,
> std::map<unsigned, std::vector<OperandInfo> > &Ops,
> - unsigned BW) :
> + unsigned BW,
> + const FixedLenDecoderEmitter *E) :
> AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
> - Parent(NULL), BestIndex(-1), BitWidth(BW) {
> + Parent(NULL), BestIndex(-1), BitWidth(BW), Emitter(E) {
> for (unsigned i = 0; i < BitWidth; ++i)
> FilterBitValues.push_back(BIT_UNFILTERED);
>
> @@ -264,7 +269,8 @@
> FilterChooser &parent) :
> AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
> Filters(), FilterBitValues(ParentFilterBitValues),
> - Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth) {
> + Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth),
> + Emitter(parent.Emitter) {
> doFilter();
> }
>
> @@ -563,17 +569,17 @@
> void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation,
> std::string Namespace) {
> o.indent(Indentation) <<
> - "static bool decode" << Namespace << "Instruction" << BitWidth
> + "static MCDisassembler::DecodeStatus decode" << Namespace << "Instruction" << BitWidth
> << "(MCInst &MI, uint" << BitWidth << "_t insn, uint64_t Address, "
> << "const void *Decoder) {\n";
> - o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n";
> + o.indent(Indentation) << " unsigned tmp = 0;\n (void)tmp;\n" << Emitter->Locals << "\n";
>
> ++Indentation; ++Indentation;
> // Emits code to decode the instructions.
> emit(o, Indentation);
>
> o << '\n';
> - o.indent(Indentation) << "return false;\n";
> + o.indent(Indentation) << "return " << Emitter->ReturnFail << ";\n";
> --Indentation; --Indentation;
>
> o.indent(Indentation) << "}\n";
> @@ -744,8 +750,8 @@
> }
>
> if (Decoder != "")
> - o.indent(Indentation) << " if (!" << Decoder
> - << "(MI, tmp, Address, Decoder)) return false;\n";
> + o.indent(Indentation) << " " << Emitter->GuardPrefix << Decoder
> + << "(MI, tmp, Address, Decoder)" << Emitter->GuardPostfix << "\n";
> else
> o.indent(Indentation) << " MI.addOperand(MCOperand::CreateImm(tmp));\n";
>
> @@ -776,15 +782,15 @@
> I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
> // If a custom instruction decoder was specified, use that.
> if (I->numFields() == 0 && I->Decoder.size()) {
> - o.indent(Indentation) << " if (!" << I->Decoder
> - << "(MI, insn, Address, Decoder)) return false;\n";
> + o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder
> + << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n";
> break;
> }
>
> emitBinaryParser(o, Indentation, *I);
> }
>
> - o.indent(Indentation) << " return true; // " << nameWithID(Opc)
> + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " << nameWithID(Opc)
> << '\n';
> o.indent(Indentation) << "}\n";
> return true;
> @@ -821,14 +827,14 @@
> I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
> // If a custom instruction decoder was specified, use that.
> if (I->numFields() == 0 && I->Decoder.size()) {
> - o.indent(Indentation) << " if (!" << I->Decoder
> - << "(MI, insn, Address, Decoder)) return false;\n";
> + o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder
> + << "(MI, insn, Address, Decoder)" << Emitter->GuardPostfix << "\n";
> break;
> }
>
> emitBinaryParser(o, Indentation, *I);
> }
> - o.indent(Indentation) << " return true; // " << nameWithID(Opc)
> + o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // " << nameWithID(Opc)
> << '\n';
> o.indent(Indentation) << "}\n";
>
> @@ -1426,7 +1432,7 @@
>
> // Emit the decoder for this namespace+width combination.
> FilterChooser FC(NumberedInstructions, I->second, Operands,
> - 8*I->first.second);
> + 8*I->first.second, this);
> FC.emitTop(o, 0, I->first.first);
> }
>
>
> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h?rev=137830&r1=137829&r2=137830&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h (original)
> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.h Wed Aug 17 12:44:15 2011
> @@ -49,9 +49,16 @@
>
> class FixedLenDecoderEmitter : public TableGenBackend {
> public:
> - FixedLenDecoderEmitter(RecordKeeper &R) :
> + FixedLenDecoderEmitter(RecordKeeper &R,
> + std::string GPrefix = "if (",
> + std::string GPostfix = " == MCDisassembler::Fail) return MCDisassembler::Fail;",
> + std::string ROK = "MCDisassembler::Success",
> + std::string RFail = "MCDisassembler::Fail",
> + std::string L = "") :
> Records(R), Target(R),
> - NumberedInstructions(Target.getInstructionsByEnumValue()) {}
> + NumberedInstructions(Target.getInstructionsByEnumValue()),
> + GuardPrefix(GPrefix), GuardPostfix(GPostfix),
> + ReturnOK(ROK), ReturnFail(RFail), Locals(L) {}
>
> // run - Output the code emitter
> void run(raw_ostream &o);
> @@ -62,7 +69,10 @@
> std::vector<const CodeGenInstruction*> NumberedInstructions;
> std::vector<unsigned> Opcodes;
> std::map<unsigned, std::vector<OperandInfo> > Operands;
> -
> +public:
> + std::string GuardPrefix, GuardPostfix;
> + std::string ReturnOK, ReturnFail;
> + std::string Locals;
> };
>
> } // end llvm namespace
>
>
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