[llvm-commits] [llvm] r138635 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp test/MC/ARM/basic-arm-instructions.s test/MC/ARM/basic-thumb-instructions.s test/MC/Disassembler/ARM/basic-arm-instructions.txt test/MC/Disassembler/ARM/thumb1.txt
Jim Grosbach
grosbach at apple.com
Fri Aug 26 11:25:31 PDT 2011
Sweet. Thanks, Owen.
Nittiness inline.
On Aug 26, 2011, at 11:09 AM, Owen Anderson wrote:
> Author: resistor
> Date: Fri Aug 26 13:09:22 2011
> New Revision: 138635
>
> URL: http://llvm.org/viewvc/llvm-project?rev=138635&view=rev
> Log:
> Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> llvm/trunk/test/MC/ARM/basic-arm-instructions.s
> llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
> llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
> llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Aug 26 13:09:22 2011
> @@ -1583,12 +1583,15 @@
> def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
> MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
> bits<4> Rd;
> - bits<12> label;
> + bits<14> label;
> let Inst{27-25} = 0b001;
> + let Inst{24} = 0;
> + let Inst{23-22} = label{13-12};
> + let Inst{21} = 0;
> let Inst{20} = 0;
> let Inst{19-16} = 0b1111;
> let Inst{15-12} = Rd;
> - let Inst{11-0} = label;
> + let Inst{11-0} = label{11-0};
> }
> def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
> 4, IIC_iALUi, []>;
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 26 13:09:22 2011
> @@ -2310,12 +2310,15 @@
>
> CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
>
> - if (Inst.getOpcode() == ARM::tADR)
> - Inst.addOperand(MCOperand::CreateReg(ARM::PC));
> - else if (Inst.getOpcode() == ARM::tADDrSPi)
> - Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> - else
> - return Fail;
> + switch(Inst.getOpcode()) {
> + case ARM::tADR:
> + break;
Not adding an explicit ARM::PC operand is intentional? Assuming so, a comment to the effect that we don't need an operand for tADR is probably in order.
> + case ARM::tADDrSPi:
> + Inst.addOperand(MCOperand::CreateReg(ARM::SP));
> + break;
> + default:
> + return Fail;
> + }
>
I don't know that it's in the actual coding standards (I couldn't find it, anyway), but the code I'm used to seeing always puts the "default" case at the top of the switch() statement.
> Inst.addOperand(MCOperand::CreateImm(imm));
> return S;
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Fri Aug 26 13:09:22 2011
> @@ -570,9 +570,18 @@
> uint32_t ARMMCCodeEmitter::
> getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const {
> - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
> - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
> - Fixups);
> + const MCOperand MO = MI.getOperand(OpIdx);
> + if (MO.isExpr())
> + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
> + Fixups);
> + int32_t offset = MO.getImm();
> + uint32_t Val = 0x2000;
> + if (offset < 0) {
> + Val = 0x1000;
> + offset *= -1;
> + }
> + Val |= offset;
> + return Val;
> }
>
> /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
> @@ -580,9 +589,11 @@
> uint32_t ARMMCCodeEmitter::
> getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const {
> - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
> - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
> - Fixups);
> + const MCOperand MO = MI.getOperand(OpIdx);
> + if (MO.isExpr())
> + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
> + Fixups);
> + return MO.getImm();
> }
>
> /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
> @@ -590,9 +601,11 @@
> uint32_t ARMMCCodeEmitter::
> getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const {
> - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
> - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
> - Fixups);
> + const MCOperand MO = MI.getOperand(OpIdx);
> + if (MO.isExpr())
> + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
> + Fixups);
> + return MO.getImm();
> }
>
> /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
>
> Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)
> +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Fri Aug 26 13:09:22 2011
> @@ -129,6 +129,8 @@
> adr r2, Lback
> adr r3, Lforward
> Lforward:
> + adr r2, #3
> + adr r2, #-3
>
> @ CHECK: Lback:
> @ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A]
> @@ -136,6 +138,8 @@
> @ CHECK: adr r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A]
> @ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12
> @ CHECK: Lforward:
> +@ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2]
> +@ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2]
>
>
> @------------------------------------------------------------------------------
>
> Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
> +++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 26 13:09:22 2011
> @@ -74,10 +74,11 @@
> @ ADR
> @------------------------------------------------------------------------------
> adr r2, _baz
> + adr r2, #3
>
> @ CHECK: adr r2, _baz @ encoding: [A,0xa2]
> @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
> -
> +@ CHECK: adr r2, #3 @ encoding: [0x03,0xa2]
>
Accidentally deleted a line of whitespace here, looks like.
> @------------------------------------------------------------------------------
> @ ASR (immediate)
>
> Modified: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions.txt Fri Aug 26 13:09:22 2011
> @@ -164,6 +164,14 @@
> 0x77 0x69 0x86 0xe0
> 0x65 0x40 0x84 0xe0
>
> +#------------------------------------------------------------------------------
> +# ADR
> +#------------------------------------------------------------------------------
> +# CHECK: add r2, pc, #3
> +# CHECK: sub r2, pc, #3
> +
> +0x03 0x20 0x8f 0xe2
> +0x03 0x20 0x4f 0xe2
>
> #------------------------------------------------------------------------------
> # AND
>
> Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138635&r1=138634&r2=138635&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Fri Aug 26 13:09:22 2011
> @@ -52,6 +52,12 @@
> 0x6a 0x44
>
> #------------------------------------------------------------------------------
> +# ADR
> +#------------------------------------------------------------------------------
> +# CHECK: adr r2, #3
> +0x03 0xa2
> +
> +#------------------------------------------------------------------------------
> # ASR (immediate)
> #------------------------------------------------------------------------------
> # CHECK: asrs r2, r3, #32
>
>
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