[llvm-commits] [llvm] r138575 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb1.txt

[Owen Anderson]

Author: resistor
Date: Thu Aug 25 13:30:18 2011
New Revision: 138575

URL: http://llvm.org/viewvc/llvm-project?rev=138575&view=rev
Log:
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138575&r1=138574&r2=138575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 25 13:30:18 2011
@@ -2539,8 +2539,8 @@
     Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
 
     CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
-    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
     CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
+    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
   } else if (Inst.getOpcode() == ARM::tADDspr) {
     unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
 

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138575&r1=138574&r2=138575&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Thu Aug 25 13:30:18 2011
@@ -29,6 +29,29 @@
 0x42 0x44
 
 #------------------------------------------------------------------------------
+# ADD (SP plus immediate)
+#------------------------------------------------------------------------------
+# CHECK: add sp, #508
+# CHECK: add sp, #4
+# CHECK: add r2, sp, #8
+# CHECK: add r2, sp, #1020
+
+0x7f 0xb0
+0x01 0xb0
+0x02 0xaa
+0xff 0xaa
+
+
+#------------------------------------------------------------------------------
+# ADD (SP plus register)
+#------------------------------------------------------------------------------
+# CHECK: add sp, r3
+# CHECK: add r2, sp, r2
+
+0x9d 0x44
+0x6a 0x44
+
+#------------------------------------------------------------------------------
 # ASR (immediate)
 #------------------------------------------------------------------------------
 # CHECK: asrs r2, r3, #32
@@ -442,6 +465,14 @@
 
 0xd1 0x1a
 
+#------------------------------------------------------------------------------
+# SUB (SP minus immediate)
+#------------------------------------------------------------------------------
+# CHECK: sub sp, #12
+# CHECK: sub sp, #508
+
+0x83 0xb0
+0xff 0xb0
 
 #------------------------------------------------------------------------------
 # SVC