[llvm-commits] [llvm] r138457 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td AsmParser/ARMAsmParser.cpp

Jim Grosbach grosbach at apple.com
Wed Aug 24 11:19:42 PDT 2011


Author: grosbach
Date: Wed Aug 24 13:19:42 2011
New Revision: 138457

URL: http://llvm.org/viewvc/llvm-project?rev=138457&view=rev
Log:
Add missing explicit writeback operand to tSTMIA_UPD.

rdar://10014745

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138457&r1=138456&r2=138457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Aug 24 13:19:42 2011
@@ -726,9 +726,10 @@
 
 // There is no non-writeback version of STM for Thumb.
 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
-def tSTMIA_UPD : T1I<(outs),
-                     (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
-                     IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>,
+def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
+                         (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
+                         AddrModeNone, 2, IIC_iStore_mu,
+                         "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
                      T1Encoding<{1,1,0,0,0,?}> {
   bits<3> Rn;
   bits<8> regs;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138457&r1=138456&r2=138457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 24 13:19:42 2011
@@ -3152,7 +3152,7 @@
   }
   case ARM::tSTMIA_UPD: {
     bool listContainsBase;
-    if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase))
+    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
       return Error(Operands[4]->getStartLoc(),
                    "registers must be in range r0-r7");
     break;





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