[llvm-commits] [llvm] r138354 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll

[Nick Lewycky]

Author: nicholas
Date: Tue Aug 23 14:01:24 2011
New Revision: 138354

URL: http://llvm.org/viewvc/llvm-project?rev=138354&view=rev
Log:
PerformSubCombine to work on integers larger than i128. Fixes a crasher.

Added:
    llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=138354&r1=138353&r2=138354&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 23 14:01:24 2011
@@ -13293,20 +13293,18 @@
   // X86 can't encode an immediate LHS of a sub. See if we can push the
   // negation into a preceding instruction.
   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
-    uint64_t Op0C = C->getSExtValue();
-
     // If the RHS of the sub is a XOR with one use and a constant, invert the
     // immediate. Then add one to the LHS of the sub so we can turn
     // X-Y -> X+~Y+1, saving one register.
     if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
         isa<ConstantSDNode>(Op1.getOperand(1))) {
-      uint64_t XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getSExtValue();
+      APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
       EVT VT = Op0.getValueType();
       SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
                                    Op1.getOperand(0),
                                    DAG.getConstant(~XorC, VT));
       return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
-                         DAG.getConstant(Op0C+1, VT));
+                         DAG.getConstant(C->getAPIntValue()+1, VT));
     }
   }
 

Added: llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll?rev=138354&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll Tue Aug 23 14:01:24 2011
@@ -0,0 +1,18 @@
+; RUN: llc -march=x86-64 -O2 < %s
+
+define void @test(i64 %add127.tr.i2686) {
+entry:
+  %conv143.i2687 = and i64 %add127.tr.i2686, 72057594037927935
+  %conv76.i2623 = zext i64 %conv143.i2687 to i128
+  %mul148.i2338 = mul i128 0, %conv76.i2623
+  %add149.i2339 = add i128 %mul148.i2338, 0
+  %add.i2303 = add i128 0, 170141183460469229370468033484042534912
+  %add6.i2270 = add i128 %add.i2303, 0
+  %sub58.i2271 = sub i128 %add6.i2270, %add149.i2339
+  %add71.i2272 = add i128 %sub58.i2271, 0
+  %add105.i2273 = add i128 %add71.i2272, 0
+  %add116.i2274 = add i128 %add105.i2273, 0
+  %shr124.i2277 = lshr i128 %add116.i2274, 56
+  %add116.tr.i2280 = trunc i128 %add116.i2274 to i64
+  ret void
+}