[llvm-commits] [llvm] r138255 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/neon.txt

Owen Anderson resistor at mac.com
Mon Aug 22 11:42:13 PDT 2011


Author: resistor
Date: Mon Aug 22 13:42:13 2011
New Revision: 138255

URL: http://llvm.org/viewvc/llvm-project?rev=138255&view=rev
Log:
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138255&r1=138254&r2=138255&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 13:42:13 2011
@@ -2769,8 +2769,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2819,8 +2822,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2876,8 +2882,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2931,8 +2940,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -2989,8 +3001,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) { 
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -3043,8 +3058,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -3103,8 +3121,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@@ -3158,8 +3179,11 @@
   }
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   Inst.addOperand(MCOperand::CreateImm(align));
-  if (Rm != 0xF && Rm != 0xD) {
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+  if (Rm != 0xF) {
+    if (Rm != 0xD)
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+    else
+      Inst.addOperand(MCOperand::CreateReg(0));
   }
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=138255&r1=138254&r2=138255&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Mon Aug 22 13:42:13 2011
@@ -1848,4 +1848,6 @@
 
 0x0 0xc 0xa0 0xf4
 # CHECK: vld1.8	{d0[]}, [r0], r0
+0x0d 0x03 0x80 0xf4
+# CHECK: vst4.8	{d0[0], d1[0], d2[0], d3[0]}, [r0]!
 





More information about the llvm-commits mailing list