[llvm-commits] [llvm] r138250 - /llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

[Owen Anderson]

Author: resistor
Date: Mon Aug 22 13:05:49 2011
New Revision: 138250

URL: http://llvm.org/viewvc/llvm-project?rev=138250&view=rev
Log:
Port another swathe of Thumb1 encoding tests over to decoding tests.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138250&r1=138249&r2=138250&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Mon Aug 22 13:05:49 2011
@@ -131,3 +131,156 @@
 0x06 0x9a
 0xff 0x9b
 
+#------------------------------------------------------------------------------
+# LDR (register)
+#------------------------------------------------------------------------------
+# CHECK: ldr r1, [r2, r3]
+
+0xd1 0x58
+
+
+#------------------------------------------------------------------------------
+# LDRB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrb r4, [r3]
+# CHECK: ldrb r5, [r6]
+# CHECK: ldrb r6, [r7, #31]
+
+0x1c 0x78
+0x35 0x78
+0xfe 0x7f
+
+
+#------------------------------------------------------------------------------
+# LDRB (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrb r6, [r4, r5]
+
+0x66 0x5d
+
+
+#------------------------------------------------------------------------------
+# LDRH (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrh r3, [r3]
+# CHECK: ldrh r4, [r6, #2]
+# CHECK: ldrh r5, [r7, #62]
+
+0x1b 0x88
+0x74 0x88
+0xfd 0x8f
+
+#------------------------------------------------------------------------------
+# LDRH (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrh r6, [r2, r6]
+
+0x96 0x5b
+
+
+#------------------------------------------------------------------------------
+# LDRSB/LDRSH
+#------------------------------------------------------------------------------
+# CHECK: ldrsb r6, [r2, r6]
+# CHECK: ldrsh r3, [r7, r1]
+
+0x96 0x57
+0x7b 0x5e
+
+#------------------------------------------------------------------------------
+# LSL (immediate)
+#------------------------------------------------------------------------------
+# CHECK: movs r4, r5
+# CHECK: lsls r4, r5, #4
+
+0x2c 0x00
+0x2c 0x01
+
+
+#------------------------------------------------------------------------------
+# LSL (register)
+#------------------------------------------------------------------------------
+# CHECK: lsls r2, r6
+
+0xb2 0x40
+
+
+#------------------------------------------------------------------------------
+# LSR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: lsrs r1, r3, #1
+# CHECK: lsrs r1, r3, #32
+
+0x59 0x08
+0x19 0x08
+
+
+#------------------------------------------------------------------------------
+# LSR (register)
+#------------------------------------------------------------------------------
+# CHECK: lsrs r2, r6
+
+0xf2 0x40
+
+#------------------------------------------------------------------------------
+# MOV (immediate)
+#------------------------------------------------------------------------------
+# CHECK: movs r2, #0
+# CHECK: movs r2, #255
+# CHECK: movs r2, #23
+
+0x00 0x22
+0xff 0x22
+0x17 0x22
+
+
+#------------------------------------------------------------------------------
+# MOV (register)
+#------------------------------------------------------------------------------
+# CHECK: mov r3, r4
+# CHECK: movs r1, r3
+
+0x23 0x46
+0x19 0x00
+
+
+#------------------------------------------------------------------------------
+# MUL
+#------------------------------------------------------------------------------
+# CHECK: muls r1, r2, r1
+# CHECK: muls r3, r4
+
+0x51 0x43
+0x63 0x43
+
+
+#------------------------------------------------------------------------------
+# MVN
+#------------------------------------------------------------------------------
+# CHECK: mvns r6, r3
+
+0xde 0x43
+
+#------------------------------------------------------------------------------
+# NEG
+#------------------------------------------------------------------------------
+# CHECK: rsbs r3, r4, #0
+
+0x63 0x42
+
+
+#------------------------------------------------------------------------------
+# NOP
+#------------------------------------------------------------------------------
+# CHECK: nop
+
+0xc0 0x46
+
+
+#------------------------------------------------------------------------------
+# ORR
+#------------------------------------------------------------------------------
+# CHECK: orrs  r3, r4
+
+0x23 0x43
+