[llvm-commits] [llvm] r138246 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb1.txt

[Owen Anderson]

Author: resistor
Date: Mon Aug 22 12:56:58 2011
New Revision: 138246

URL: http://llvm.org/viewvc/llvm-project?rev=138246&view=rev
Log:
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode.  Add more tests.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138246&r1=138245&r2=138246&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Aug 22 12:56:58 2011
@@ -2322,7 +2322,7 @@
 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
                                   uint64_t Address, const void *Decoder) {
   Inst.addOperand(MCOperand::CreateReg(ARM::SP));
-  Inst.addOperand(MCOperand::CreateImm(Val << 2));
+  Inst.addOperand(MCOperand::CreateImm(Val));
 
   return Success;
 }

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt?rev=138246&r1=138245&r2=138246&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb1.txt Mon Aug 22 12:56:58 2011
@@ -101,3 +101,33 @@
 
 0x6c 0x40
 
+#------------------------------------------------------------------------------
+# LDM
+#------------------------------------------------------------------------------
+# CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
+# CHECK: ldm r2!, {r1, r3, r4, r5, r7}
+# CHECK: ldm r1, {r1}
+
+0xff 0xcb
+0xba 0xca
+0x02 0xc9
+
+
+#------------------------------------------------------------------------------
+# LDR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldr r1, [r5]
+# CHECK: ldr r2, [r6, #32]
+# CHECK: ldr r3, [r7, #124]
+# CHECK: ldr r1, [sp]
+# CHECK: ldr r2, [sp, #24]
+# CHECK: ldr r3, [sp, #1020]
+
+
+0x29 0x68
+0x32 0x6a
+0xfb 0x6f
+0x00 0x99
+0x06 0x9a
+0xff 0x9b
+