[llvm-commits] [llvm] r138163 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
Chad Rosier
mcrosier at apple.com
Fri Aug 19 17:17:25 PDT 2011
Author: mcrosier
Date: Fri Aug 19 19:17:25 2011
New Revision: 138163
URL: http://llvm.org/viewvc/llvm-project?rev=138163&view=rev
Log:
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=138163&r1=138162&r2=138163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Aug 19 19:17:25 2011
@@ -628,7 +628,7 @@
bool SPRDest = ARM::SPRRegClass.contains(DestReg);
bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
- unsigned Opc;
+ unsigned Opc = 0;
if (SPRDest && SPRSrc) {
Opc = ARM::VMOVS;
@@ -668,17 +668,38 @@
Opc = ARM::VORRq;
else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQQ;
- else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
- Opc = ARM::VMOVQQQQ;
- else
- llvm_unreachable("Impossible reg-to-reg copy");
- MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
- MIB.addReg(SrcReg, getKillRegState(KillSrc));
- if (Opc == ARM::VORRq)
+ if (Opc) {
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
MIB.addReg(SrcReg, getKillRegState(KillSrc));
- if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
- AddDefaultPred(MIB);
+ if (Opc == ARM::VORRq)
+ MIB.addReg(SrcReg, getKillRegState(KillSrc));
+ if (Opc != ARM::VMOVQQ)
+ AddDefaultPred(MIB);
+ return;
+ }
+
+ // Expand the MOVQQQQ pseudo instruction in place.
+ if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
+ const TargetRegisterInfo *TRI = &getRegisterInfo();
+ assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
+ for (unsigned i = ARM::qsub_0, e = ARM::qsub_3 + 1; i != e; ++i) {
+ unsigned Dst = TRI->getSubReg(DestReg, i);
+ unsigned Src = TRI->getSubReg(SrcReg, i);
+ MachineInstrBuilder Mov =
+ AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
+ .addReg(Dst, RegState::Define)
+ .addReg(Src, getKillRegState(KillSrc))
+ .addReg(Src, getKillRegState(KillSrc)));
+ if (i == ARM::qsub_3) {
+ Mov->addRegisterDefined(DestReg, TRI);
+ if (KillSrc)
+ Mov->addRegisterKilled(SrcReg, TRI);
+ }
+ }
+ return;
+ }
+ llvm_unreachable("Impossible reg-to-reg copy");
}
static const
Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=138163&r1=138162&r2=138163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Aug 19 19:17:25 2011
@@ -998,52 +998,6 @@
return true;
}
- case ARM::VMOVQQQQ: {
- unsigned DstReg = MI.getOperand(0).getReg();
- bool DstIsDead = MI.getOperand(0).isDead();
- unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
- unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
- unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
- unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
- unsigned SrcReg = MI.getOperand(1).getReg();
- bool SrcIsKill = MI.getOperand(1).isKill();
- unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
- unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
- unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
- unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
- MachineInstrBuilder Mov0 =
- AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get(ARM::VORRq))
- .addReg(Dst0,
- RegState::Define | getDeadRegState(DstIsDead))
- .addReg(Src0, getKillRegState(SrcIsKill))
- .addReg(Src0, getKillRegState(SrcIsKill)));
- MachineInstrBuilder Mov1 =
- AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get(ARM::VORRq))
- .addReg(Dst1,
- RegState::Define | getDeadRegState(DstIsDead))
- .addReg(Src1, getKillRegState(SrcIsKill))
- .addReg(Src1, getKillRegState(SrcIsKill)));
- MachineInstrBuilder Mov2 =
- AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get(ARM::VORRq))
- .addReg(Dst2,
- RegState::Define | getDeadRegState(DstIsDead))
- .addReg(Src2, getKillRegState(SrcIsKill))
- .addReg(Src2, getKillRegState(SrcIsKill)));
- MachineInstrBuilder Mov3 =
- AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get(ARM::VORRq))
- .addReg(Dst3,
- RegState::Define | getDeadRegState(DstIsDead))
- .addReg(Src3, getKillRegState(SrcIsKill))
- .addReg(Src3, getKillRegState(SrcIsKill)));
- TransferImpOps(MI, Mov0, Mov3);
- MI.eraseFromParent();
- return true;
- }
-
case ARM::VLDMQIA: {
unsigned NewOpc = ARM::VLDMDIA;
MachineInstrBuilder MIB =
Modified: llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll?rev=138163&r1=138162&r2=138163&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll Fri Aug 19 19:17:25 2011
@@ -1,7 +1,6 @@
; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0 -o -
-; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
-; Make sure that it gets expanded; otherwise, the compile fails when trying
-; to print the pseudo-instruction.
+; Make sure that the VMOVQQQQ pseudo instruction is handled properly
+; by codegen.
define void @test_vmovqqqq_pseudo() nounwind ssp {
entry:
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