[llvm-commits] [llvm] r137657 - /llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt

[Owen Anderson]

Author: resistor
Date: Mon Aug 15 16:29:01 2011
New Revision: 137657

URL: http://llvm.org/viewvc/llvm-project?rev=137657&view=rev
Log:
Add some more comprehensive VFP decoding tests.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt

Added: llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt?rev=137657&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/fp-encoding.txt Mon Aug 15 16:29:01 2011
@@ -0,0 +1,213 @@
+# RUN: llvm-mc -triple armv7-apple-darwin -disassemble < %s | FileCheck %s
+
+0xa0 0x0b 0x71 0xee
+# CHECK: vadd.f64        d16, d17, d16
+
+0x80 0x0a 0x30 0xee
+# CHECK: vadd.f32        s0, s1, s0
+
+0xe0 0x0b 0x71 0xee
+# CHECK: vsub.f64        d16, d17, d16
+
+0xc0 0x0a 0x30 0xee
+# CHECK: vsub.f32        s0, s1, s0
+
+0xa0 0x0b 0xc1 0xee
+# CHECK: vdiv.f64        d16, d17, d16
+
+0x80 0x0a 0x80 0xee
+# CHECK: vdiv.f32        s0, s1, s0
+
+0xa0 0x0b 0x61 0xee
+# CHECK: vmul.f64        d16, d17, d16
+
+0x80 0x0a 0x20 0xee
+# CHECK: vmul.f32        s0, s1, s0
+
+0xe0 0x0b 0x61 0xee
+# CHECK: vnmul.f64       d16, d17, d16
+
+0xc0 0x0a 0x20 0xee
+# CHECK: vnmul.f32       s0, s1, s0
+
+0xe0 0x1b 0xf4 0xee
+# CHECK: vcmpe.f64       d17, d16
+
+0xc0 0x0a 0xf4 0xee
+# CHECK: vcmpe.f32       s1, s0
+
+0xe0 0x0b 0xf0 0xee
+# CHECK: vabs.f64        d16, d16
+
+0xc0 0x0a 0xb0 0xee
+# CHECK: vabs.f32        s0, s0
+
+0xe0 0x0b 0xb7 0xee
+# CHECK: vcvt.f32.f64    s0, d16
+
+0xc0 0x0a 0xf7 0xee
+# CHECK: vcvt.f64.f32    d16, s0
+
+0x60 0x0b 0xf1 0xee
+# CHECK: vneg.f64        d16, d16
+
+0x40 0x0a 0xb1 0xee
+# CHECK: vneg.f32        s0, s0
+
+0xe0 0x0b 0xf1 0xee
+# CHECK: vsqrt.f64       d16, d16
+
+0xc0 0x0a 0xb1 0xee
+# CHECK: vsqrt.f32       s0, s0
+
+0xc0 0x0b 0xf8 0xee
+# CHECK: vcvt.f64.s32    d16, s0
+
+0xc0 0x0a 0xb8 0xee
+# CHECK: vcvt.f32.s32    s0, s0
+
+0x40 0x0b 0xf8 0xee
+# CHECK: vcvt.f64.u32    d16, s0
+
+0x40 0x0a 0xb8 0xee
+# CHECK: vcvt.f32.u32    s0, s0
+
+0xe0 0x0b 0xbd 0xee
+# CHECK: vcvt.s32.f64    s0, d16
+
+0xc0 0x0a 0xbd 0xee
+# CHECK: vcvt.s32.f32    s0, s0
+
+0xe0 0x0b 0xbc 0xee
+# CHECK: vcvt.u32.f64    s0, d16
+
+0xc0 0x0a 0xbc 0xee
+# CHECK: vcvt.u32.f32    s0, s0
+
+0xa1 0x0b 0x42 0xee
+# CHECK: vmla.f64        d16, d18, d17
+
+0x00 0x0a 0x41 0xee
+# CHECK: vmla.f32        s1, s2, s0
+
+0xe1 0x0b 0x42 0xee
+# CHECK: vmls.f64        d16, d18, d17
+
+0x40 0x0a 0x41 0xee
+# CHECK: vmls.f32        s1, s2, s0
+
+0xe1 0x0b 0x52 0xee
+# CHECK: vnmla.f64       d16, d18, d17
+
+0x40 0x0a 0x51 0xee
+# CHECK: vnmla.f32       s1, s2, s0
+
+0xa1 0x0b 0x52 0xee
+# CHECK: vnmls.f64       d16, d18, d17
+
+0x00 0x0a 0x51 0xee
+# CHECK: vnmls.f32       s1, s2, s0
+
+0x60 0x0b 0xf1 0x1e
+# CHECK: vnegne.f64      d16, d16
+
+0x10 0x0a 0x00 0x1e
+0x10 0x1a 0x00 0x0e
+# CHECK: vmovne  s0, r0
+# CHECK: vmoveq  s0, r1
+
+0x10 0x0a 0xf1 0xee
+# CHECK: vmrs    r0, fpscr
+0x10 0x0a 0xf8 0xee
+# CHECK: vmrs  r0, fpexc
+0x10 0x0a 0xf0 0xee
+# CHECK: vmrs  r0, fpsid
+
+0x10 0x0a 0xe1 0xee
+# CHECK: vmsr    fpscr, r0
+0x10 0x0a 0xe8 0xee
+# CHECK: vmsr  fpexc, r0
+0x10 0x0a 0xe0 0xee
+# CHECK: vmsr  fpsid, r0
+
+0x10 0x0a 0x00 0xee
+0x90 0x1a 0x00 0xee
+0x10 0x2a 0x01 0xee
+0x90 0x3a 0x01 0xee
+# CHECK: vmov    s0, r0
+# CHECK: vmov    s1, r1
+# CHECK: vmov    s2, r2
+# CHECK: vmov    s3, r3
+
+0x10 0x0a 0x10 0xee
+0x90 0x1a 0x10 0xee
+0x10 0x2a 0x11 0xee
+0x90 0x3a 0x11 0xee
+# CHECK: vmov    r0, s0
+# CHECK: vmov    r1, s1
+# CHECK: vmov    r2, s2
+# CHECK: vmov    r3, s3
+
+0x30 0x0b 0x51 0xec
+# CHECK: vmov    r0, r1, d16
+
+0x00 0x1b 0xd0 0xed
+# CHECK: vldr.64	d17, [r0]
+
+0x08 0x1b 0x92 0xed
+0x08 0x1b 0x12 0xed
+# CHECK: vldr.64	d1, [r2, #32]
+# CHECK: vldr.64	d1, [r2, #-32]
+
+0x00 0x2b 0x93 0xed
+# CHECK: vldr.64 d2, [r3]
+
+0x00 0x3b 0x9f 0xed
+# CHECK: vldr.64 d3, [pc]
+
+0x00 0x6a 0xd0 0xed
+# CHECK: vldr.32	s13, [r0]
+
+0x08 0x0a 0xd2 0xed
+0x08 0x0a 0x52 0xed
+# CHECK: vldr.32	s1, [r2, #32]
+# CHECK: vldr.32	s1, [r2, #-32]
+
+0x00 0x1a 0x93 0xed
+# CHECK: vldr.32 s2, [r3]
+
+0x00 0x2a 0xdf 0xed
+# CHECK: vldr.32 s5, [pc]
+
+0x00 0x4b 0x81 0xed
+0x06 0x4b 0x81 0xed
+0x06 0x4b 0x01 0xed
+# CHECK: vstr.64 d4, [r1]
+# CHECK: vstr.64 d4, [r1, #24]
+# CHECK: vstr.64 d4, [r1, #-24]
+
+0x00 0x2a 0x81 0xed
+0x06 0x2a 0x81 0xed
+0x06 0x2a 0x01 0xed
+# CHECK: vstr.32 s4, [r1]
+# CHECK: vstr.32 s4, [r1, #24]
+# CHECK: vstr.32 s4, [r1, #-24]
+
+0x0c 0x2b 0x91 0xec
+0x06 0x1a 0x91 0xec
+# CHECK: vldmia  r1, {d2, d3, d4, d5, d6, d7}
+# CHECK: vldmia  r1, {s2, s3, s4, s5, s6, s7}
+
+0x0c 0x2b 0x81 0xec
+0x06 0x1a 0x81 0xec
+# CHECK: vstmia  r1, {d2, d3, d4, d5, d6, d7}
+# CHECK: vstmia  r1, {s2, s3, s4, s5, s6, s7}
+
+0x40 0x0b 0xbd 0xee
+0x60 0x0a 0xbd 0xee
+0x40 0x0b 0xbc 0xee
+0x60 0x0a 0xbc 0xee
+# CHECK: vcvtr.s32.f64  s0, d0
+# CHECK: vcvtr.s32.f32  s0, s1
+# CHECK: vcvtr.u32.f64  s0, d0
+# CHECK: vcvtr.u32.f32  s0, s1