[llvm-commits] [llvm] r137367 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/arm-memory-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Thu Aug 11 17:05:09 2011
New Revision: 137367

URL: http://llvm.org/viewvc/llvm-project?rev=137367&view=rev
Log:
ARM load shifted register pre-index fix shift value asm parser encoding.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/arm-memory-instructions.s

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=137367&r1=137366&r2=137367&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Aug 11 17:05:09 2011
@@ -830,7 +830,7 @@
       // For register offset, we encode the shift type and negation flag
       // here.
       Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
-                              0, Mem.ShiftType);
+                              Mem.ShiftImm, Mem.ShiftType);
     }
     Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
     Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));

Modified: llvm/trunk/test/MC/ARM/arm-memory-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-memory-instructions.s?rev=137367&r1=137366&r2=137367&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm-memory-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm-memory-instructions.s Thu Aug 11 17:05:09 2011
@@ -38,6 +38,7 @@
         ldr r2, [r5, -r3]
         ldr r1, [r5, r9]!
         ldr r6, [r7, -r8]!
+        ldr r1, [r0, r2, lsr #3]!
         ldr r5, [r9], r2
         ldr r4, [r3], -r6
         ldr r3, [r8, -r2, lsl #15]
@@ -47,6 +48,7 @@
 @ CHECK: ldr	r2, [r5, -r3]           @ encoding: [0x03,0x20,0x15,0xe7]
 @ CHECK: ldr	r1, [r5, r9]!           @ encoding: [0x09,0x10,0xb5,0xe7]
 @ CHECK: ldr	r6, [r7, -r8]!          @ encoding: [0x08,0x60,0x37,0xe7]
+@ CHECK: ldr	r1, [r0, r2, lsr #3]!   @ encoding: [0xa2,0x11,0xb0,0xe7]
 @ CHECK: ldr	r5, [r9], r2            @ encoding: [0x02,0x50,0x99,0xe6]
 @ CHECK: ldr	r4, [r3], -r6           @ encoding: [0x06,0x40,0x13,0xe6]
 @ CHECK: ldr	r3, [r8, -r2, lsl #15]  @ encoding: [0x82,0x37,0x18,0xe7]