[llvm-commits] [llvm] r137323 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt

[Owen Anderson]

Author: resistor
Date: Thu Aug 11 13:55:42 2011
New Revision: 137323

URL: http://llvm.org/viewvc/llvm-project?rev=137323&view=rev
Log:
Tighten operand decoding of addrmode2 instruction.  The offset register cannot be PC.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137323&r1=137322&r2=137323&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Aug 11 13:55:42 2011
@@ -625,7 +625,7 @@
   let PrintMethod = "printAddrMode2Operand";
   let DecoderMethod = "DecodeSORegMemOperand";
   let ParserMatchClass = MemRegOffsetAsmOperand;
-  let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$shift);
+  let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
 }
 
 // postidx_imm8 := +/- [0,255]

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137323&r1=137322&r2=137323&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 11 13:55:42 2011
@@ -979,7 +979,7 @@
     idx_mode = ARMII::IndexModePost;
 
   if (reg) {
-    if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
+    if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
     switch( fieldFromInstruction32(Insn, 5, 2)) {
       case 0:

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt?rev=137323&r1=137322&r2=137323&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt Thu Aug 11 13:55:42 2011
@@ -1,11 +1,10 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 # -------------------------------------------------------------------------------------------------
 # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
 # -------------------------------------------------------------------------------------------------
-# 
+#
 # if m == 15 then UNPREDICTABLE
 0x8f 0x60 0xb7 0xe7