[llvm-commits] [llvm] r137180 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-LSL-regform.txt test/MC/Disassembler/ARM/invalid-RSC-arm.txt

[Owen Anderson]

Author: resistor
Date: Tue Aug  9 18:33:27 2011
New Revision: 137180

URL: http://llvm.org/viewvc/llvm-project?rev=137180&view=rev
Log:
Tighten operand checking of register-shifted-register operands.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137180&r1=137179&r2=137180&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug  9 18:33:27 2011
@@ -439,7 +439,7 @@
   let PrintMethod = "printSORegRegOperand";
   let DecoderMethod = "DecodeSORegRegOperand";
   let ParserMatchClass = ShiftedRegAsmOperand;
-  let MIOperandInfo = (ops GPR, GPR, i32imm);
+  let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
 }
 
 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
@@ -2541,9 +2541,9 @@
   let Inst{15-12} = Rd;
 }
 
-def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
+def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
                 DPSoRegRegFrm, IIC_iMOVsr,
-                "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_reg:$src)]>,
+                "mov", "\t$Rd, $src", [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>,
                 UnaryDP {
   bits<4> Rd;
   bits<12> src;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137180&r1=137179&r2=137180&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug  9 18:33:27 2011
@@ -683,8 +683,8 @@
   unsigned Rs = fieldFromInstruction32(Val, 8, 4);
 
   // Register-register
-  DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
-  DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
+  if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
+  if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
 
   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
   switch (type) {

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt?rev=137180&r1=137179&r2=137180&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt Tue Aug  9 18:33:27 2011
@@ -1,8 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 # -------------------------------------------------------------------------------------------------
 # | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0|
 # -------------------------------------------------------------------------------------------------

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt?rev=137180&r1=137179&r2=137180&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt Tue Aug  9 18:33:27 2011
@@ -1,8 +1,7 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-# XFAIL: *
 
 # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
 # -------------------------------------------------------------------------------------------------
 # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
 # -------------------------------------------------------------------------------------------------