[llvm-commits] [llvm] r137156 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/arm-tests.txt

[Benjamin Kramer]

Author: d0k
Date: Tue Aug  9 17:02:50 2011
New Revision: 137156

URL: http://llvm.org/viewvc/llvm-project?rev=137156&view=rev
Log:
ARM Disassembler: sign extend branch immediates.

Not sure about BLXi, but this is what the old disassembler did.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137156&r1=137155&r2=137156&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug  9 17:02:50 2011
@@ -1214,11 +1214,11 @@
   if (pred == 0xF) {
     Inst.setOpcode(ARM::BLXi);
     imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
-    Inst.addOperand(MCOperand::CreateImm(imm));
+    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
     return true;
   }
 
-  Inst.addOperand(MCOperand::CreateImm(imm));
+  Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
   if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
 
   return true;

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=137156&r1=137155&r2=137156&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Aug  9 17:02:50 2011
@@ -248,6 +248,9 @@
 # CHECK:	stc2	p2, cr4, [r9], {157}
 0x9d 0x42 0x89 0xfc
 
+# CHECK:	bne #-24
+0xfa 0xff 0xff 0x1a
+
 # CHECK:	blx	#60
 0x0f 0x00 0x00 0xfa