[llvm-commits] [patch][arm] Implement support for the Q, R and H modifiers

[Jakob Stoklund Olesen]

On Aug 9, 2011, at 12:52 PM, Eric Christopher wrote:

>> How hard would it be to add the constraint that the registers have to be sequential? If doing it I would probably try it by creating a new pseudo reg class that alias the regular R registers and use those as operands to the inline asm. Is that what you had in mind?
>> 
> 
> Pretty much exactly.

The hard part is convincing isel to do this since i64 is not a legal type.

You can play tricks with a REG_SEQUENCE node feeding an MVT::untyped edge to the INLINEASM.

>> So, I guess this is a judgment call. The current patch allows us to handle some inline asm but causes us to miscompile others that we currently reject.
> 
> I'm going to say we should add them for now. People that are using it incorrectly may get a hard to debug problem, but the use case you guys have totally makes sense and isn't necessarily easy to rewrite to make more sense.

Agreed. Actually, there is a good chance they will get assembler errors instead of miscompiles.

/jakob