[llvm-commits] [llvm] r137114 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-cvt.ll

[Eli Friedman]

On Mon, Aug 8, 2011 at 10:48 PM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> Author: bruno
> Date: Tue Aug  9 00:48:01 2011
> New Revision: 137114
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137114&view=rev
> Log:
> Handle sitofp between v4f64 <- v4i32. Fix PR10559
>
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/test/CodeGen/X86/avx-cvt.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=137114&r1=137113&r2=137114&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug  9 00:48:01 2011
> @@ -969,6 +969,9 @@
>     setOperationAction(ISD::SINT_TO_FP,         MVT::v8i32, Legal);
>     setOperationAction(ISD::FP_ROUND,           MVT::v4f32, Legal);
>
> +    // sint_to_fp between different vector types needs custom handling
> +    setOperationAction(ISD::SINT_TO_FP,         MVT::v4i32, Custom);
> +
>     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v4f64,  Custom);
>     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v4i64,  Custom);
>     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v8f32,  Custom);
> @@ -7078,6 +7081,24 @@
>  SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
>                                            SelectionDAG &DAG) const {
>   EVT SrcVT = Op.getOperand(0).getValueType();
> +  EVT DstVT = Op.getValueType();
> +  DebugLoc dl = Op.getDebugLoc();
> +
> +  if (SrcVT.isVector() && DstVT.isVector()) {
> +    unsigned SrcVTSize = SrcVT.getSizeInBits();
> +    unsigned DstVTSize = DstVT.getSizeInBits();
> +
> +    // Support directly by the target
> +    if (SrcVTSize == DstVTSize)
> +      return Op;
> +
> +    // Handle v4f64 = sitofp v4i32
> +    if (DstVT != MVT::v4f64 && SrcVT != MVT::v4i32)
> +      return SDValue();
> +
> +    SDValue V = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Op.getOperand(0));
> +    return DAG.getNode(ISD::FP_EXTEND, dl, DstVT, V);
> +  }

Aren't there accuracy issues with this approach?  A float can't
precisely represent every possible i32.

-Eli