[llvm-commits] [patch][arm] Implement support for the Q, R and H modifiers

[Eric Christopher]

Hi Rafael,

On Aug 8, 2011, at 10:30 AM, Rafael Ávila de Espíndola wrote:

> 
>> Yes, each group of machine operands on an INLINEASM begin with an immediate describing the group.
> 
> Cool. The attached patch uses InlineAsm::getNumOperandRegisters. is it ok.
> 
>> In this case, it is probably good enough to check that OpNum+1 exists and is a register.
> 
> The previous patch does that if you prefer it :-)

Sorry about the delay in responding, I've just returned from vacation. 

I have some concerns about this patch as is - basically I'm worried about subtle miscompiles based on how gcc does register allocation for multiple reg wide values versus how llvm does it. In the gcc case it will (as far as I know) assign consecutive registers for these sorts of values, but there's no guarantee that llvm will do this. This means that in the case of stm/ldm instructions with the 'Q' and 'R' modifiers that we'd get registers that weren't meant, leading to subtle problems that users would need to debug. When we get support for assigning values into consecutive registers this won't be a problem.

What are your thoughts?

-eric