[llvm-commits] [patch][arm] Implement support for the Q, R and H modifiers

[Jakob Stoklund Olesen]

On Aug 4, 2011, at 5:14 PM, Evan Cheng wrote:

> +    case 'H': // The highest-numbered register of a pair.
> +    case 'R': // The most significant register of a pair.
> +    case 'Q': { // The least significant register of a pair.
> +      unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
> +      const MachineOperand &MO = MI->getOperand(RegOp);
> 
> This assumes the operand is the low register of the pair, i.e. even. Is that guaranteed?

No.

We don't allocate even/odd pairs for 64-bit values. We don't even allocate consecutive registers.

Without that constraint, I can't imagine a use for the 'H' modifier?

/jakob