[llvm-commits] [llvm] r135471 - /llvm/trunk/test/Transforms/InstSimplify/compare.ll

[Duncan Sands]

Hi Nick,

> If you feed 'sub nsw' an input which sign-wraps, then you've encountered
> undefined behaviour. That's what I'm claiming always happens; this test *always*
> puts the sub in a situation where it needs to do a signed wrap.

you are right, but I think it would be better to fix the test rather than just
removing it.  I suggest introducing a new argument i32 %Z and defining B to be
%B = or i32 2147483648, %Z.

Ciao, Duncan.

>
> %Y doesn't feed into the sub, so let's look at i16 %X. %A has 16-bits of 0
> followed by 16-bits of unknown. %B has the sign bit set, then 15 bits of 0,
> followed by the same 16-bits of unknown.
>
> Visualized in hex with free variables pqrs, that's 0000pqrs - 7000pqrs =
> 70000000. If I understand the definition of nsw correctly, we aren't allowed to
> wrap that way.
>
>>
>> Ciao, Duncan.
>>
>>>
>>> Modified:
>>> llvm/trunk/test/Transforms/InstSimplify/compare.ll
>>>
>>> Modified: llvm/trunk/test/Transforms/InstSimplify/compare.ll
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/compare.ll?rev=135471&r1=135470&r2=135471&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/test/Transforms/InstSimplify/compare.ll (original)
>>> +++ llvm/trunk/test/Transforms/InstSimplify/compare.ll Tue Jul 19 03:22:57 2011
>>> @@ -283,17 +283,6 @@
>>> ret i1 %E
>>> }
>>>
>>> -; CHECK: @srem4
>>> -; CHECK-NEXT: ret i1 false
>>> -define i1 @srem4(i16 %X, i32 %Y) {
>>> - %A = zext i16 %X to i32
>>> - %B = or i32 2147483648, %A
>>> - %C = sub nsw i32 %A, %B
>>> - %D = srem i32 %C, %Y
>>> - %E = icmp slt i32 %D, 0
>>> - ret i1 %E
>>> -}
>>> -
>>> define i1 @udiv1(i32 %X) {
>>> ; CHECK: @udiv1
>>> %A = udiv i32 %X, 1000000
>>>
>>>
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>