[llvm-commits] [llvm] r135979 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

[Evan Cheng]

Author: evancheng
Date: Mon Jul 25 16:32:49 2011
New Revision: 135979

URL: http://llvm.org/viewvc/llvm-project?rev=135979&view=rev
Log:
Fix more MC layering violations.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=135979&r1=135978&r2=135979&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 16:32:49 2011
@@ -153,6 +153,11 @@
 };
 } // end anonymous namespace
 
+namespace llvm {
+  // FIXME: TableGen this?
+  extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
+}
+
 namespace {
 
 /// ARMOperand - Instances of this class represent a parsed ARM machine
@@ -971,9 +976,11 @@
                 SMLoc StartLoc, SMLoc EndLoc) {
     KindTy Kind = RegisterList;
 
-    if (ARM::DPRRegClass.contains(Regs.front().first))
+    if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
+        contains(Regs.front().first))
       Kind = DPRRegisterList;
-    else if (ARM::SPRRegClass.contains(Regs.front().first))
+    else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
+             contains(Regs.front().first))
       Kind = SPRRegisterList;
 
     ARMOperand *Op = new ARMOperand(Kind);