[llvm-commits] [PATCH] TableGen CodeEmitter Backend for JITCodeEmitter

[Logan Chien]

Dear all,

  With commit r134539, the CodeEmitter backend of TableGen will not generate
case for
pseudo instruction.  It seems that r134539 assumed that the pseudo
instruction will
be lowered before calling CodeEmitter::getBinaryCodeForInstr.  Thus,
getBinaryCodeForInstr
will report a fatal error if it gets a pseudo instruction.

  However, ARMCodeEmitter does not lower the pseudo instruction before
calling
getBinaryCodeForInstr, and ARMCodeEmitter will no longer work after r134539.
With this patch, we will generate case for pseudo instruction for
CodeEmitter (but not
MCCodeEmitter) just like what was done before.

  Please review.  Thanks!

Sincerely,
Logan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20110722/f75bb530/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-Fix-ARMCodeEmitter-pseudo-instruction-encoder.patch
Type: application/octet-stream
Size: 1280 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20110722/f75bb530/attachment.obj>