[llvm-commits] [PATCH] Atomic NAND options

[Cameron McInally]

Ah, great point. I have x86 tunnel-vision.

If you guys would like to go ahead with the change, I would be willing
to modify the other targets.

On Thursday, July 14, 2011, Jim Grosbach <grosbach at apple.com> wrote:
>
> On Jul 14, 2011, at 9:29 AM, Chris Lattner wrote:
>
>>
>> On Jul 14, 2011, at 8:03 AM, Cameron McInally wrote:
>>
>>> Hey Guys,
>>>
>>> I have been working on Atomic NAND. Here is a patch that allows the
>>> compiler writer to select a [NOT AND] implementation, while retaining
>>> [NEGATE and AND] as the default implementation for those that do not
>>> want the current GCC implementation (i.e. GCC v4.4 and later).
>>
>> Hi Cameron,
>>
>> Is there a reason to support the broken pre-gcc-4.4 implementation at all?
>>
>
> If we change (either optionally or unconditionally), we should also make sure to change all targets that implement the intrinsics, not just X86. It would be really nasty for the behaviour to be target specific.
>
> -Jim
>
>>
>>>
>>> upstream/llvm> svn diff
>>> Index: lib/Target/X86/X86ISelLowering.cpp
>>> ===================================================================
>>> --- lib/Target/X86/X86ISelLowering.cpp    (revision 135054)
>>> +++ lib/Target/X86/X86ISelLowering.cpp    (working copy)
>>> @@ -9710,7 +9710,8 @@
>>>                                                         unsigned notOpc,
>>>                                                         unsigned EAXreg,
>>>
>>> TargetRegisterClass *RC,
>>> -                                                       bool invSrc) const {
>>> +                                                       bool invSrc,
>>> +                                bool invRes) const {
>>>    // For the atomic bitwise operator, we generate
>>>    //   thisMBB:
>>>    //   newMBB:
>>> @@ -9783,13 +9784,20 @@
>>>    MIB.addReg(tt);
>>>    (*MIB).addOperand(*argOpers[valArgIndx]);
>>>
>>> +  unsigned tr = F->getRegInfo().createVirtualRegister(RC);
>>> +  if (invRes) {
>>> +    MIB = BuildMI(newMBB, dl, TII->get(notOpc), tr).addReg(t2);
>>> +  }
>>> +  else
>>> +    tr = t2;
>>> +
>>>    MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
>>>    MIB.addReg(t1);
>>>
>>>    MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
>>>    for (int i=0; i <= lastAddrIndx; ++i)
>>>      (*MIB).addOperand(*argOpers[i]);
>>> -  MIB.addReg(t2);
>>> +  MIB.addReg(tr);
>>>    assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
>>>    (*MIB).setMemRefs(bInstr->memoperands_begin(),
>>>                      bInstr->memoperands_end());
>>> @@ -9812,7 +9820,8 @@
>>>                                                         unsigned regOpcH,
>>>                                                         unsigned immOpcL,
>>>                                                         unsigned immOpcH,
>>> -                                                       bool invSrc) const {
>>> +                                                       bool invSrc,
>>> +                                bool invRes) const {
>>>    // For the atomic bitwise operator, we generate
>>>    //   thisMBB (instructions are in pairs, except cmpxchg8b)
>>>    //     ld t1,t2 = [bitinstr.addr]
>>> @@ -9939,15 +9948,26 @@
>>>      MIB.addReg(t2);
>>>    (*MIB).addOperand(*argOpers[valArgIndx + 1]);
>>>
>>> +  unsigned trl = F->getRegInfo().createVirtualRegister(RC);
>>> +  unsigned trh = F->getRegInfo().createVirtualRegister(RC);
>>> +  if (invRes) {
>>> +    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), trl).addReg(t5);
>>> +    MIB = BuildMI(