[llvm-commits] [llvm] r135024 - /llvm/trunk/lib/Target/ARM/README.txt

[Evan Cheng]

Author: evancheng
Date: Tue Jul 12 20:33:00 2011
New Revision: 135024

URL: http://llvm.org/viewvc/llvm-project?rev=135024&view=rev
Log:
Add an entry.

Modified:
    llvm/trunk/lib/Target/ARM/README.txt

Modified: llvm/trunk/lib/Target/ARM/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=135024&r1=135023&r2=135024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/README.txt (original)
+++ llvm/trunk/lib/Target/ARM/README.txt Tue Jul 12 20:33:00 2011
@@ -681,3 +681,21 @@
     str    r1, [r0]
 
 //===---------------------------------------------------------------------===//
+
+Improve codegen for select's:
+if (x != 0) x = 1
+if (x == 1) x = 1
+
+ARM codegen used to look like this:
+       mov     r1, r0
+       cmp     r1, #1
+       mov     r0, #0
+       moveq   r0, #1
+
+The naive lowering select between two different values. It should recognize the
+test is equality test so it's more a conditional move rather than a select:
+       cmp     r0, #1
+       movne   r0, #0
+
+Currently this is a ARM specific dag combine. We probably should make it into a
+target-neutral one.