[llvm-commits] [llvm] r134569 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp ARMTargetMachine.h MCTargetDesc/ARMMCTargetDesc.cpp MCTargetDesc/ARMMCTargetDesc.h
Eli Friedman
eli.friedman at gmail.com
Wed Jul 6 20:04:50 PDT 2011
On Wed, Jul 6, 2011 at 5:08 PM, Evan Cheng <evan.cheng at apple.com> wrote:
> Author: evancheng
> Date: Wed Jul 6 19:08:19 2011
> New Revision: 134569
>
> URL: http://llvm.org/viewvc/llvm-project?rev=134569&view=rev
> Log:
> Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
This appears to be making tests fail on multiple bots ( for example,
http://google1.osuosl.org:8011/builders/llvm-x86_64-linux/builds/7701
).
-Eli
> Modified:
> llvm/trunk/lib/Target/ARM/ARM.td
> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.td Wed Jul 6 19:08:19 2011
> @@ -27,7 +27,7 @@
> "Enable VFP3 instructions">;
> def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
> "Enable NEON instructions">;
> -def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
> +def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
> "Enable Thumb2 instructions">;
> def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
> "Does not support ARM mode execution">;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jul 6 19:08:19 2011
> @@ -37,7 +37,7 @@
> cl::desc("Disallow all unaligned memory accesses"));
>
> ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
> - const std::string &FS, bool isT)
> + const std::string &FS)
> : ARMGenSubtargetInfo()
> , ARMArchVersion(V4)
> , ARMProcFamily(Others)
> @@ -46,8 +46,8 @@
> , SlowFPVMLx(false)
> , HasVMLxForwarding(false)
> , SlowFPBrcc(false)
> - , IsThumb(isT)
> - , ThumbMode(Thumb1)
> + , IsThumb(false)
> + , HasThumb2(false)
> , NoARM(false)
> , PostRAScheduler(false)
> , IsR9Reserved(ReserveR9)
> @@ -68,65 +68,8 @@
> , TargetTriple(TT)
> , TargetABI(ARM_ABI_APCS) {
> // Determine default and user specified characteristics
> -
> - // When no arch is specified either by CPU or by attributes, make the default
> - // ARMv4T.
> - const char *ARMArchFeature = "";
> if (CPUString.empty())
> CPUString = "generic";
> - if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
> - ARMArchVersion = V4T;
> - ARMArchFeature = "+v4t";
> - }
> -
> - // Set the boolean corresponding to the current target triple, or the default
> - // if one cannot be determined, to true.
> - unsigned Len = TT.length();
> - unsigned Idx = 0;
> -
> - if (Len >= 5 && TT.substr(0, 4) == "armv")
> - Idx = 4;
> - else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
> - IsThumb = true;
> - if (Len >= 7 && TT[5] == 'v')
> - Idx = 6;
> - }
> - if (Idx) {
> - unsigned SubVer = TT[Idx];
> - if (SubVer >= '7' && SubVer <= '9') {
> - ARMArchVersion = V7A;
> - ARMArchFeature = "+v7a";
> - if (Len >= Idx+2 && TT[Idx+1] == 'm') {
> - ARMArchVersion = V7M;
> - ARMArchFeature = "+v7m";
> - } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
> - ARMArchVersion = V7EM;
> - ARMArchFeature = "+v7em";
> - }
> - } else if (SubVer == '6') {
> - ARMArchVersion = V6;
> - ARMArchFeature = "+v6";
> - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
> - ARMArchVersion = V6T2;
> - ARMArchFeature = "+v6t2";
> - }
> - } else if (SubVer == '5') {
> - ARMArchVersion = V5T;
> - ARMArchFeature = "+v5t";
> - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
> - ARMArchVersion = V5TE;
> - ARMArchFeature = "+v5te";
> - }
> - } else if (SubVer == '4') {
> - if (Len >= Idx+2 && TT[Idx+1] == 't') {
> - ARMArchVersion = V4T;
> - ARMArchFeature = "+v4t";
> - } else {
> - ARMArchVersion = V4;
> - ARMArchFeature = "";
> - }
> - }
> - }
>
> if (TT.find("eabi") != std::string::npos)
> TargetABI = ARM_ABI_AAPCS;
> @@ -134,12 +77,20 @@
> // Insert the architecture feature derived from the target triple into the
> // feature string. This is important for setting features that are implied
> // based on the architecture version.
> - std::string FSWithArch = std::string(ARMArchFeature);
> - if (FSWithArch.empty())
> - FSWithArch = FS;
> - else if (!FS.empty())
> - FSWithArch = FSWithArch + "," + FS;
> - ParseSubtargetFeatures(FSWithArch, CPUString);
> + std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb);
> + if (!FS.empty()) {
> + if (!ArchFS.empty())
> + ArchFS = ArchFS + "," + FS;
> + else
> + ArchFS = FS;
> + }
> +
> + ParseSubtargetFeatures(ArchFS, CPUString);
> +
> + // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
> + // ARM version or CPU and then remove this.
> + if (ARMArchVersion < V6T2 && hasThumb2())
> + ARMArchVersion = V6T2;
>
> // Initialize scheduling itinerary for the specified CPU.
> InstrItins = getInstrItineraryForCPU(CPUString);
> @@ -147,12 +98,6 @@
> // After parsing Itineraries, set ItinData.IssueWidth.
> computeIssueWidth();
>
> - // Thumb2 implies at least V6T2.
> - if (ARMArchVersion >= V6T2)
> - ThumbMode = Thumb2;
> - else if (ThumbMode >= Thumb2)
> - ARMArchVersion = V6T2;
> -
> if (isAAPCS_ABI())
> stackAlignment = 8;
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jul 6 19:08:19 2011
> @@ -14,6 +14,7 @@
> #ifndef ARMSUBTARGET_H
> #define ARMSUBTARGET_H
>
> +#include "MCTargetDesc/ARMMCTargetDesc.h"
> #include "llvm/Target/TargetSubtargetInfo.h"
> #include "llvm/MC/MCInstrItineraries.h"
> #include "llvm/ADT/Triple.h"
> @@ -39,11 +40,6 @@
> None, VFPv2, VFPv3, NEON
> };
>
> - enum ThumbTypeEnum {
> - Thumb1,
> - Thumb2
> - };
> -
> /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
> /// V6, V6T2, V7A, V7M, V7EM.
> ARMArchEnum ARMArchVersion;
> @@ -73,8 +69,8 @@
> /// IsThumb - True if we are in thumb mode, false if in ARM mode.
> bool IsThumb;
>
> - /// ThumbMode - Indicates supported Thumb version.
> - ThumbTypeEnum ThumbMode;
> + /// HasThumb2 - True if Thumb2 instructions are supported.
> + bool HasThumb2;
>
> /// NoARM - True if subtarget does not support ARM mode execution.
> bool NoARM;
> @@ -161,7 +157,7 @@
> /// of the specified triple.
> ///
> ARMSubtarget(const std::string &TT, const std::string &CPU,
> - const std::string &FS, bool isThumb);
> + const std::string &FS);
>
> /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
> /// that still makes it profitable to inline the call.
> @@ -217,9 +213,9 @@
> bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
>
> bool isThumb() const { return IsThumb; }
> - bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
> - bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
> - bool hasThumb2() const { return ThumbMode >= Thumb2; }
> + bool isThumb1Only() const { return IsThumb && !HasThumb2; }
> + bool isThumb2() const { return IsThumb && HasThumb2; }
> + bool hasThumb2() const { return HasThumb2; }
>
> bool isR9Reserved() const { return IsR9Reserved; }
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jul 6 19:08:19 2011
> @@ -79,10 +79,9 @@
> ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
> const std::string &TT,
> const std::string &CPU,
> - const std::string &FS,
> - bool isThumb)
> + const std::string &FS)
> : LLVMTargetMachine(T, TT),
> - Subtarget(TT, CPU, FS, isThumb),
> + Subtarget(TT, CPU, FS),
> JITInfo(),
> InstrItins(Subtarget.getInstrItineraryData()) {
> DefRelocModel = getRelocationModel();
> @@ -95,7 +94,7 @@
> ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget),
> + : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget),
> DataLayout(Subtarget.isAPCS_ABI() ?
> std::string("e-p:32:32-f64:32:64-i64:32:64-"
> "v128:32:128-v64:32:64-n32") :
> @@ -113,7 +112,7 @@
> ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : ARMBaseTargetMachine(T, TT, CPU, FS, true),
> + : ARMBaseTargetMachine(T, TT, CPU, FS),
> InstrInfo(Subtarget.hasThumb2()
> ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
> : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Jul 6 19:08:19 2011
> @@ -41,8 +41,7 @@
>
> public:
> ARMBaseTargetMachine(const Target &T, const std::string &TT,
> - const std::string &CPU, const std::string &FS,
> - bool isThumb);
> + const std::string &CPU, const std::string &FS);
>
> virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
> virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Jul 6 19:08:19 2011
> @@ -72,3 +72,49 @@
> TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
> createARMMCSubtargetInfo);
> }
> +
> +std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) {
> + // Set the boolean corresponding to the current target triple, or the default
> + // if one cannot be determined, to true.
> + unsigned Len = TT.size();
> + unsigned Idx = 0;
> +
> + if (Len >= 5 && TT.substr(0, 4) == "armv")
> + Idx = 4;
> + else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
> + IsThumb = true;
> + if (Len >= 7 && TT[5] == 'v')
> + Idx = 6;
> + }
> +
> + std::string ARMArchFeature;
> + if (Idx) {
> + unsigned SubVer = TT[Idx];
> + if (SubVer >= '7' && SubVer <= '9') {
> + ARMArchFeature = "+v7a";
> + if (Len >= Idx+2 && TT[Idx+1] == 'm') {
> + ARMArchFeature = "+v7m";
> + } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
> + ARMArchFeature = "+v7em";
> + }
> + } else if (SubVer == '6') {
> + ARMArchFeature = "+v6";
> + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
> + ARMArchFeature = "+v6t2";
> + }
> + } else if (SubVer == '5') {
> + ARMArchFeature = "+v5t";
> + if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
> + ARMArchFeature = "+v5te";
> + }
> + } else if (SubVer == '4') {
> + if (Len >= Idx+2 && TT[Idx+1] == 't') {
> + ARMArchFeature = "+v4t";
> + } else {
> + ARMArchFeature = "";
> + }
> + }
> + }
> +
> + return ARMArchFeature;
> +}
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134569&r1=134568&r2=134569&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Wed Jul 6 19:08:19 2011
> @@ -14,10 +14,18 @@
> #ifndef ARMMCTARGETDESC_H
> #define ARMMCTARGETDESC_H
>
> +#include <string>
> +
> namespace llvm {
> class Target;
> +class StringRef;
>
> extern Target TheARMTarget, TheThumbTarget;
> +
> +namespace ARM_MC {
> + std::string ParseARMTriple(StringRef TT, bool &IsThumb);
> +}
> +
> } // End llvm namespace
>
> // Defines symbolic names for ARM registers. This defines a mapping from
>
>
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